Simulation Results: edn/edn1

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.15 %
  • code
  • 84.91 %
  • assert
  • 97.14 %
  • func
  • 79.41 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 89.31 %
  • toggle
  • 95.83 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.900s 19.292us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.080s 88.492us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 28.538us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.540s 851.067us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.110s 55.156us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.310s 54.673us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 28.538us 1 1 100.00
edn_csr_aliasing 1.110s 55.156us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.180s 107.330us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.180s 107.330us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.180s 107.330us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.690s 54.894us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.860s 73.285us 1 1 100.00
errs 1 1 100.00
edn_err 0.860s 20.076us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 35.733us 1 1 100.00
edn_disable_auto_req_mode 0.920s 56.857us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.190s 137.348us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.950s 65.362us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.730s 70.232us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.030s 251.941us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.030s 251.941us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.080s 88.492us 1 1 100.00
edn_csr_rw 0.810s 28.538us 1 1 100.00
edn_csr_aliasing 1.110s 55.156us 1 1 100.00
edn_same_csr_outstanding 0.830s 50.301us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.080s 88.492us 1 1 100.00
edn_csr_rw 0.810s 28.538us 1 1 100.00
edn_csr_aliasing 1.110s 55.156us 1 1 100.00
edn_same_csr_outstanding 0.830s 50.301us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 2.140s 109.514us 1 1 100.00
edn_sec_cm 2.080s 563.003us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 101.084us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.860s 73.285us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.080s 563.003us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.080s 563.003us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.080s 563.003us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.080s 563.003us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.860s 73.285us 1 1 100.00
edn_sec_cm 2.080s 563.003us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.860s 73.285us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.140s 109.514us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 37.350s 3711.582us 1 1 100.00