| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
91.67% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 57.950s | 77.014us | 1 | 1 | 100.00 | |
| smoke_hw | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke_hw | 8.990s | 17.649us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 19.050s | 197.666us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.590s | 143.507us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_bit_bash | 41.790s | 2736.785us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_aliasing | 20.060s | 856.651us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_mem_rw_with_rand_reset | 7.400s | 51.656us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| flash_ctrl_csr_rw | 8.590s | 143.507us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 20.060s | 856.651us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_walk | 7.130s | 84.052us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_partial_access | 6.040s | 19.681us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sw_op | 1 | 1 | 100.00 | |||
| flash_ctrl_sw_op | 10.970s | 55.339us | 1 | 1 | 100.00 | |
| host_read_direct | 1 | 1 | 100.00 | |||
| flash_ctrl_host_dir_rd | 32.490s | 55.118us | 1 | 1 | 100.00 | |
| rma_hw_if | 3 | 3 | 100.00 | |||
| flash_ctrl_hw_rma | 1137.920s | 169109.182us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_rma_reset | 737.310s | 160182.949us | 1 | 1 | 100.00 | |
| flash_ctrl_lcmgr_intg | 5.640s | 57.460us | 1 | 1 | 100.00 | |
| host_controller_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_host_ctrl_arb | 1397.350s | 337143.044us | 1 | 1 | 100.00 | |
| erase_suspend | 1 | 1 | 100.00 | |||
| flash_ctrl_erase_suspend | 153.930s | 23213.426us | 1 | 1 | 100.00 | |
| program_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_prog_reset | 5.300s | 71.215us | 1 | 1 | 100.00 | |
| full_memory_access | 1 | 1 | 100.00 | |||
| flash_ctrl_full_mem_access | 1930.790s | 458227.590us | 1 | 1 | 100.00 | |
| rd_buff_eviction | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_buff_evict | 71.010s | 2811.251us | 1 | 1 | 100.00 | |
| rd_buff_eviction_w_ecc | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_evict | 12.030s | 51.817us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_evict_all_en | 16.830s | 52.427us | 1 | 1 | 100.00 | |
| flash_ctrl_re_evict | 13.550s | 60.978us | 1 | 1 | 100.00 | |
| host_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 72.670s | 126.971us | 1 | 1 | 100.00 | |
| host_interleave | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 72.670s | 126.971us | 1 | 1 | 100.00 | |
| memory_protection | 1 | 1 | 100.00 | |||
| flash_ctrl_mp_regions | 168.020s | 20611.477us | 1 | 1 | 100.00 | |
| fetch_code | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 12.870s | 778.300us | 1 | 1 | 100.00 | |
| all_partitions | 1 | 1 | 100.00 | |||
| flash_ctrl_rand_ops | 195.420s | 186.504us | 1 | 1 | 100.00 | |
| error_mp | 1 | 1 | 100.00 | |||
| flash_ctrl_error_mp | 483.290s | 18521.320us | 1 | 1 | 100.00 | |
| error_prog_win | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_win | 319.370s | 3734.748us | 1 | 1 | 100.00 | |
| error_prog_type | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_type | 779.370s | 438.239us | 1 | 1 | 100.00 | |
| error_read_seed | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_read_seed_err | 6.300s | 78.849us | 1 | 1 | 100.00 | |
| read_write_overflow | 1 | 1 | 100.00 | |||
| flash_ctrl_oversize_error | 101.510s | 2111.722us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 8.570s | 20.831us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 1 | 1 | 100.00 | |||
| flash_ctrl_connect | 8.080s | 155.247us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| flash_ctrl_stress_all | 488.310s | 224.025us | 1 | 1 | 100.00 | |
| secret_partition | 2 | 2 | 100.00 | |||
| flash_ctrl_hw_sec_otp | 95.910s | 2068.068us | 1 | 1 | 100.00 | |
| flash_ctrl_otp_reset | 39.640s | 76.917us | 1 | 1 | 100.00 | |
| isolation_partition | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1137.920s | 169109.182us | 1 | 1 | 100.00 | |
| interrupts | 4 | 4 | 100.00 | |||
| flash_ctrl_intr_rd | 74.320s | 698.734us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr | 48.980s | 4218.384us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_rd_slow_flash | 171.450s | 23918.909us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr_slow_flash | 129.940s | 24267.019us | 1 | 1 | 100.00 | |
| invalid_op | 1 | 1 | 100.00 | |||
| flash_ctrl_invalid_op | 48.840s | 875.559us | 1 | 1 | 100.00 | |
| mid_op_rst | 1 | 1 | 100.00 | |||
| flash_ctrl_mid_op_rst | 33.260s | 7520.809us | 1 | 1 | 100.00 | |
| double_bit_err | 5 | 5 | 100.00 | |||
| flash_ctrl_read_word_sweep_derr | 11.480s | 77.847us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_derr | 89.900s | 741.445us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 134.160s | 6162.373us | 1 | 1 | 100.00 | |
| flash_ctrl_derr_detect | 100.740s | 3709.558us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 318.520s | 10561.898us | 1 | 1 | 100.00 | |
| single_bit_err | 3 | 3 | 100.00 | |||
| flash_ctrl_read_word_sweep_serr | 11.060s | 80.752us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_serr | 80.510s | 2014.534us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_serr | 160.690s | 7569.547us | 1 | 1 | 100.00 | |
| singlebit_err_counter | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_counter | 55.900s | 4511.567us | 1 | 1 | 100.00 | |
| singlebit_err_address | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_address | 55.050s | 765.141us | 1 | 1 | 100.00 | |
| scramble | 5 | 5 | 100.00 | |||
| flash_ctrl_wo | 156.500s | 25514.997us | 1 | 1 | 100.00 | |
| flash_ctrl_write_word_sweep | 8.260s | 171.369us | 1 | 1 | 100.00 | |
| flash_ctrl_read_word_sweep | 9.620s | 26.173us | 1 | 1 | 100.00 | |
| flash_ctrl_ro | 69.650s | 1051.258us | 1 | 1 | 100.00 | |
| flash_ctrl_rw | 381.810s | 5450.222us | 1 | 1 | 100.00 | |
| filesystem_support | 1 | 1 | 100.00 | |||
| flash_ctrl_fs_sup | 22.360s | 308.269us | 1 | 1 | 100.00 | |
| rma_write_process_error | 2 | 2 | 100.00 | |||
| flash_ctrl_rma_err | 574.440s | 40399.613us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_prog_rma_wipe_err | 85.190s | 10041.111us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| flash_ctrl_alert_test | 5.880s | 47.781us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| flash_ctrl_intr_test | 5.580s | 76.473us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 7.800s | 75.806us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 7.800s | 75.806us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 19.050s | 197.666us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 8.590s | 143.507us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 20.060s | 856.651us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 14.470s | 810.551us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 19.050s | 197.666us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 8.590s | 143.507us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 20.060s | 856.651us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 14.470s | 810.551us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 36.920s | 154.438us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 36.920s | 154.438us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 36.920s | 154.438us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 36.920s | 154.438us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors_with_csr_rw | 27.840s | 514.577us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| flash_ctrl_tl_intg_err | 193.690s | 398.806us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_cm | 1508.210s | 4445.099us | 1 | 1 | 100.00 | |
| sec_cm_reg_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 193.690s | 398.806us | 1 | 1 | 100.00 | |
| sec_cm_host_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 193.690s | 398.806us | 1 | 1 | 100.00 | |
| sec_cm_mem_bus_integrity | 1 | 2 | 50.00 | |||
| flash_ctrl_rd_intg | 18.910s | 241.511us | 1 | 1 | 100.00 | |
| flash_ctrl_wr_intg | 8.330s | 38.315us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 57.950s | 77.014us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 4 | 4 | 100.00 | |||
| flash_ctrl_otp_reset | 39.640s | 76.917us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 8.570s | 20.831us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_info_access | 60.250s | 10444.776us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 8.080s | 155.247us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_config_regwen | 5.740s | 22.468us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.590s | 143.507us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 36.920s | 154.438us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.590s | 143.507us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 36.920s | 154.438us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.590s | 143.507us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 36.920s | 154.438us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_global_esc | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 8.570s | 20.831us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_local_esc | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 18.910s | 241.511us | 1 | 1 | 100.00 | |
| flash_ctrl_access_after_disable | 5.860s | 24.007us | 1 | 1 | 100.00 | |
| sec_cm_mem_addr_infection | 1 | 1 | 100.00 | |||
| flash_ctrl_host_addr_infection | 12.980s | 27.771us | 1 | 1 | 100.00 | |
| sec_cm_mem_disable_config_mubi | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 8.570s | 20.831us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 12.870s | 778.300us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| flash_ctrl_rw | 381.810s | 5450.222us | 1 | 1 | 100.00 | |
| sec_cm_mem_integrity | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_serr | 160.690s | 7569.547us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 134.160s | 6162.373us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 318.520s | 10561.898us | 1 | 1 | 100.00 | |
| sec_cm_rma_entry_mem_sec_wipe | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1137.920s | 169109.182us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1508.210s | 4445.099us | 1 | 1 | 100.00 | |
| sec_cm_phy_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1508.210s | 4445.099us | 1 | 1 | 100.00 | |
| sec_cm_phy_prog_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1508.210s | 4445.099us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1508.210s | 4445.099us | 1 | 1 | 100.00 | |
| sec_cm_phy_arbiter_ctrl_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb_redun | 9.880s | 967.260us | 1 | 1 | 100.00 | |
| sec_cm_phy_host_grant_ctrl_consistency | 0 | 1 | 0.00 | |||
| flash_ctrl_phy_host_grant_err | 7.040s | 52.005us | 0 | 1 | 0.00 | |
| sec_cm_phy_ack_ctrl_consistency | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_ack_consistency | 7.210s | 64.689us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1508.210s | 4445.099us | 1 | 1 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1508.210s | 4445.099us | 1 | 1 | 100.00 | |
| sec_cm_prog_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1508.210s | 4445.099us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| asymmetric_read_path | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_ooo | 20.490s | 325.923us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| flash_ctrl_basic_rw | 295.850s | 628.055us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (flash_ctrl_otf_scoreboard.sv:368) [wdata_page0_comp_bank1] *: obs:exp b9_*_1b977806_343ea6da:ac_*_17486ecf_b* mismatch!! | ||||
| flash_ctrl_wr_intg | 37967292876453026410994868195899599393369438081072921840320506221697629062388 | 120 |
UVM_ERROR @ 38315.1 ns: (flash_ctrl_otf_scoreboard.sv:368) [wdata_page0_comp_bank1] 0: obs:exp b9_1_1b977806_343ea6da:ac_1_17486ecf_b2671858 mismatch!!
UVM_INFO @ 38315.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' | ||||
| flash_ctrl_phy_host_grant_err | 30646157670592278136031861465279368415708422012318898843223348828464394962469 | 125 |
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
UVM_ERROR @ 52005.3 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 52005.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|