| V1 |
|
100.00% |
| V2 |
|
94.12% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 1.190s | 93.859us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 0.770s | 61.318us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 0.790s | 44.188us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 0.860s | 36.902us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.670s | 65.516us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 0.640s | 15.451us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 1.270s | 510.029us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 0.760s | 18.444us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.210s | 38.653us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 0.640s | 15.451us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.760s | 18.444us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 0.800s | 30.268us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 0.660s | 25.331us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 0.940s | 23.296us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 1.090s | 177.658us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 2.420s | 117.918us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 1.480s | 38.774us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 10.050s | 2128.456us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 1.910s | 365.047us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 1.020s | 304.406us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| gpio_stress_all | 18.440s | 2512.865us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.710s | 13.365us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.780s | 16.094us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.560s | 174.390us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.560s | 174.390us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.640s | 15.451us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.790s | 38.375us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.760s | 18.444us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.670s | 65.516us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.640s | 15.451us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.790s | 38.375us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.760s | 18.444us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.670s | 65.516us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_sec_cm | 0.920s | 422.834us | 1 | 1 | 100.00 | |
| gpio_tl_intg_err | 1.130s | 290.103us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 1.130s | 290.103us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 0.670s | 15.692us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 1.770s | 72.487us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| gpio_stress_all | 43577298568583313057064647131095300362095956185218658663258168291148231683234 | 717 |
UVM_ERROR @ 2512865237 ps: (gpio_scoreboard.sv:216) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 3289218444 [0xc40d7d8c])
UVM_INFO @ 2512865237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* | ||||
| gpio_stress_all_with_rand_reset | 4988843794719449442599047288463730026552873425473136560565440061255302856214 | 78 |
UVM_FATAL @ 72487154 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 72487154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|