Simulation Results: hmac

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.70 %
  • code
  • 96.90 %
  • assert
  • 96.70 %
  • func
  • 42.51 %
  • line
  • 99.59 %
  • branch
  • 98.68 %
  • cond
  • 95.05 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.810s 122.709us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.750s 33.361us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.890s 108.228us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.150s 2093.547us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.480s 168.389us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.840s 26.791us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.890s 108.228us 1 1 100.00
hmac_csr_aliasing 5.480s 168.389us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 68.340s 10352.275us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 56.450s 1467.537us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 229.150s 7597.970us 1 1 100.00
hmac_test_sha384_vectors 368.850s 41099.339us 1 1 100.00
hmac_test_sha512_vectors 19.120s 1168.174us 1 1 100.00
hmac_test_hmac256_vectors 8.810s 1188.146us 1 1 100.00
hmac_test_hmac384_vectors 6.600s 245.905us 1 1 100.00
hmac_test_hmac512_vectors 9.110s 1431.179us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 13.660s 2366.417us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 632.140s 81382.851us 1 1 100.00
error 1 1 100.00
hmac_error 2.270s 53.996us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 6.540s 533.315us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.810s 122.709us 1 1 100.00
hmac_long_msg 68.340s 10352.275us 1 1 100.00
hmac_back_pressure 56.450s 1467.537us 1 1 100.00
hmac_datapath_stress 632.140s 81382.851us 1 1 100.00
hmac_burst_wr 13.660s 2366.417us 1 1 100.00
hmac_stress_all 33.040s 7598.560us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.810s 122.709us 1 1 100.00
hmac_long_msg 68.340s 10352.275us 1 1 100.00
hmac_back_pressure 56.450s 1467.537us 1 1 100.00
hmac_datapath_stress 632.140s 81382.851us 1 1 100.00
hmac_wipe_secret 6.540s 533.315us 1 1 100.00
hmac_test_sha256_vectors 229.150s 7597.970us 1 1 100.00
hmac_test_sha384_vectors 368.850s 41099.339us 1 1 100.00
hmac_test_sha512_vectors 19.120s 1168.174us 1 1 100.00
hmac_test_hmac256_vectors 8.810s 1188.146us 1 1 100.00
hmac_test_hmac384_vectors 6.600s 245.905us 1 1 100.00
hmac_test_hmac512_vectors 9.110s 1431.179us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.810s 122.709us 1 1 100.00
hmac_long_msg 68.340s 10352.275us 1 1 100.00
hmac_back_pressure 56.450s 1467.537us 1 1 100.00
hmac_datapath_stress 632.140s 81382.851us 1 1 100.00
hmac_burst_wr 13.660s 2366.417us 1 1 100.00
hmac_error 2.270s 53.996us 1 1 100.00
hmac_wipe_secret 6.540s 533.315us 1 1 100.00
hmac_test_sha256_vectors 229.150s 7597.970us 1 1 100.00
hmac_test_sha384_vectors 368.850s 41099.339us 1 1 100.00
hmac_test_sha512_vectors 19.120s 1168.174us 1 1 100.00
hmac_test_hmac256_vectors 8.810s 1188.146us 1 1 100.00
hmac_test_hmac384_vectors 6.600s 245.905us 1 1 100.00
hmac_test_hmac512_vectors 9.110s 1431.179us 1 1 100.00
hmac_stress_all 33.040s 7598.560us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 33.040s 7598.560us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.570s 12.390us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.620s 13.680us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.460s 65.554us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.460s 65.554us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.750s 33.361us 1 1 100.00
hmac_csr_rw 0.890s 108.228us 1 1 100.00
hmac_csr_aliasing 5.480s 168.389us 1 1 100.00
hmac_same_csr_outstanding 1.710s 89.560us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.750s 33.361us 1 1 100.00
hmac_csr_rw 0.890s 108.228us 1 1 100.00
hmac_csr_aliasing 5.480s 168.389us 1 1 100.00
hmac_same_csr_outstanding 1.710s 89.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.750s 141.013us 1 1 100.00
hmac_tl_intg_err 1.360s 81.864us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.360s 81.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.810s 122.709us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.570s 709.986us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 18.730s 23067.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.960s 26.218us 1 1 100.00