Simulation Results: i2c

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.99 %
  • code
  • 81.76 %
  • assert
  • 95.98 %
  • func
  • 80.23 %
  • line
  • 96.69 %
  • branch
  • 92.76 %
  • cond
  • 86.47 %
  • toggle
  • 89.45 %
  • FSM
  • 43.45 %
Validation stages
V1
100.00%
V2
90.24%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 51.630s 6675.262us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 9.040s 897.934us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.780s 25.151us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.850s 25.567us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.500s 381.085us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.400s 385.391us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.880s 120.780us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.850s 25.567us 1 1 100.00
i2c_csr_aliasing 1.400s 385.391us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.050s 58.795us 0 1 0.00
host_stress_all 1 1 100.00
i2c_host_stress_all 119.330s 12959.491us 1 1 100.00
host_maxperf 1 1 100.00
i2c_host_perf 73.940s 7943.453us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.640s 233.068us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 223.680s 19320.842us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 77.570s 1824.213us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.160s 231.724us 1 1 100.00
i2c_host_fifo_fmt_empty 4.920s 822.437us 1 1 100.00
i2c_host_fifo_reset_rx 2.340s 572.759us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 61.000s 12541.550us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 15.140s 501.273us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.910s 68.574us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.550s 1954.614us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 92.000s 17469.384us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.580s 8700.626us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 47.540s 6204.642us 1 1 100.00
i2c_target_intr_smoke 5.150s 1240.213us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.450s 479.033us 1 1 100.00
i2c_target_fifo_reset_tx 1.680s 241.685us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 859.340s 69107.971us 1 1 100.00
i2c_target_stress_rd 47.540s 6204.642us 1 1 100.00
i2c_target_intr_stress_wr 21.800s 43653.793us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.840s 6046.462us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 86.990s 2708.149us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 6.460s 14950.633us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.740s 796.732us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.150s 651.921us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.290s 673.120us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 73.940s 7943.453us 1 1 100.00
i2c_host_perf_precise 1.310s 65.646us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 15.140s 501.273us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 4.230s 205.215us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 1.760s 1642.863us 1 1 100.00
i2c_target_nack_acqfull_addr 2.120s 1513.903us 1 1 100.00
i2c_target_nack_txstretch 1.290s 738.060us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 10.780s 1014.907us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 2.720s 2189.762us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.730s 16.131us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.840s 15.472us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.490s 115.068us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.490s 115.068us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.780s 25.151us 1 1 100.00
i2c_csr_rw 0.850s 25.567us 1 1 100.00
i2c_csr_aliasing 1.400s 385.391us 1 1 100.00
i2c_same_csr_outstanding 1.110s 59.463us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.780s 25.151us 1 1 100.00
i2c_csr_rw 0.850s 25.567us 1 1 100.00
i2c_csr_aliasing 1.400s 385.391us 1 1 100.00
i2c_same_csr_outstanding 1.110s 59.463us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.650s 301.509us 1 1 100.00
i2c_sec_cm 0.910s 135.038us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.650s 301.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 11.120s 3674.487us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.540s 218.582us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 22.340s 6754.734us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 68560053514009474826652648548527736994063575778739507437922824814311165558692 110
UVM_ERROR @ 58794628 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 58794628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_mode_toggle 18609426802203439196013343638771540640213011031792532849091981363491733902362 81
UVM_ERROR @ 68573529 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 68573529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 61229581486184785363010238201925201933324516707150294109405641677979614196659 84
UVM_ERROR @ 1954614230 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1954614230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 98263755175039891082354464242558657848942241068067739133256698376498114808324 78
UVM_ERROR @ 218581737 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 218581737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 101075200238049875503321625568187421262673992338023946900582007293822070756626 116
UVM_ERROR @ 3674486666 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3674486666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 29356106201948124408458707358074099571187571703509810501966932141720018248943 112
UVM_ERROR @ 6754734012 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6754734012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 92597633984204322707875011037654438222376160916831048438833036395146065079590 78
UVM_ERROR @ 738060305 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 738060305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---