Simulation Results: kmac/unmasked

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.01 %
  • code
  • 88.63 %
  • assert
  • 97.90 %
  • func
  • 92.50 %
  • line
  • 97.43 %
  • branch
  • 95.20 %
  • cond
  • 90.30 %
  • toggle
  • 99.87 %
  • FSM
  • 60.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 44.200s 2881.203us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.060s 45.656us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.890s 42.875us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 7.320s 2428.449us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 4.150s 911.899us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.880s 361.946us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.890s 42.875us 1 1 100.00
kmac_csr_aliasing 4.150s 911.899us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.830s 40.349us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.050s 17.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2292.390s 1035149.399us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 556.000s 35185.776us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 30.150s 3517.204us 1 1 100.00
kmac_test_vectors_sha3_256 28.220s 3134.781us 1 1 100.00
kmac_test_vectors_sha3_384 21.670s 1741.694us 1 1 100.00
kmac_test_vectors_sha3_512 530.440s 9208.949us 1 1 100.00
kmac_test_vectors_shake_128 121.420s 25441.085us 1 1 100.00
kmac_test_vectors_shake_256 1499.990s 122059.088us 1 1 100.00
kmac_test_vectors_kmac 1.890s 196.200us 1 1 100.00
kmac_test_vectors_kmac_xof 1.540s 76.893us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 196.850s 52127.463us 1 1 100.00
app 1 1 100.00
kmac_app 76.040s 5949.852us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 25.730s 1556.056us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 30.360s 2357.785us 1 1 100.00
error 1 1 100.00
kmac_error 218.820s 15316.585us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 6.390s 9078.428us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 2.810s 62.318us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 7.570s 380.375us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 16.410s 919.689us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 27.060s 16382.599us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.030s 54.551us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 872.320s 15363.571us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.710s 12.816us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.840s 26.551us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.800s 179.609us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.800s 179.609us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.060s 45.656us 1 1 100.00
kmac_csr_rw 0.890s 42.875us 1 1 100.00
kmac_csr_aliasing 4.150s 911.899us 1 1 100.00
kmac_same_csr_outstanding 1.300s 51.806us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.060s 45.656us 1 1 100.00
kmac_csr_rw 0.890s 42.875us 1 1 100.00
kmac_csr_aliasing 4.150s 911.899us 1 1 100.00
kmac_same_csr_outstanding 1.300s 51.806us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.500s 81.443us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.500s 81.443us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.500s 81.443us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.500s 81.443us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.160s 176.669us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 30.180s 16749.346us 1 1 100.00
kmac_tl_intg_err 3.570s 435.230us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.570s 435.230us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.030s 54.551us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 44.200s 2881.203us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 196.850s 52127.463us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.500s 81.443us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 30.180s 16749.346us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 30.180s 16749.346us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 30.180s 16749.346us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 44.200s 2881.203us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.030s 54.551us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 30.180s 16749.346us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 70.790s 5143.246us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 44.200s 2881.203us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 36.290s 9725.021us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 20158233441068386197021322240265188763029460466435377556738890025421194259458 152
UVM_ERROR @ 9725021298 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9725021298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---