Simulation Results: lc_ctrl/volatile_unlock_disabled

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.50 %
  • code
  • 84.32 %
  • assert
  • 94.13 %
  • func
  • 93.06 %
  • line
  • 97.21 %
  • branch
  • 93.97 %
  • cond
  • 79.59 %
  • toggle
  • 88.21 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.640s 98.298us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.030s 20.831us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.990s 48.993us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.300s 20.256us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 107.844us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.480s 286.439us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.990s 48.993us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 107.844us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.500s 194.441us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.140s 171.188us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.020s 37.910us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.320s 248.819us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.540s 271.221us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.590s 9236.896us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.540s 271.221us 1 1 100.00
lc_ctrl_prog_failure 2.320s 248.819us 1 1 100.00
lc_ctrl_errors 7.590s 9236.896us 1 1 100.00
lc_ctrl_security_escalation 6.050s 932.189us 1 1 100.00
lc_ctrl_jtag_state_failure 54.250s 5556.295us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.750s 865.661us 1 1 100.00
lc_ctrl_jtag_errors 67.530s 42430.546us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.930s 113.070us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.170s 1138.686us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.750s 865.661us 1 1 100.00
lc_ctrl_jtag_errors 67.530s 42430.546us 1 1 100.00
lc_ctrl_jtag_access 8.260s 3863.193us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 27.360s 2766.561us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.160s 259.200us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.610s 54.644us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.200s 343.395us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.920s 1198.936us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.650s 73.930us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.950s 783.247us 1 1 100.00
lc_ctrl_jtag_alert_test 1.060s 54.297us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.180s 1240.344us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.850s 45.289us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 50.710s 4556.101us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.100s 29.459us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.050s 641.568us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.050s 641.568us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 20.831us 1 1 100.00
lc_ctrl_csr_rw 0.990s 48.993us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 107.844us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.520s 86.404us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 20.831us 1 1 100.00
lc_ctrl_csr_rw 0.990s 48.993us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 107.844us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.520s 86.404us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.210s 228.176us 1 1 100.00
lc_ctrl_tl_intg_err 1.950s 226.615us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.950s 226.615us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.140s 171.188us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.540s 271.221us 1 1 100.00
lc_ctrl_sec_cm 6.210s 228.176us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.540s 271.221us 1 1 100.00
lc_ctrl_sec_cm 6.210s 228.176us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.540s 271.221us 1 1 100.00
lc_ctrl_sec_cm 6.210s 228.176us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.540s 271.221us 1 1 100.00
lc_ctrl_sec_cm 6.210s 228.176us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.540s 271.221us 1 1 100.00
lc_ctrl_sec_cm 6.210s 228.176us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.540s 271.221us 1 1 100.00
lc_ctrl_sec_cm 6.210s 228.176us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.540s 271.221us 1 1 100.00
lc_ctrl_sec_cm 6.210s 228.176us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.540s 271.221us 1 1 100.00
lc_ctrl_sec_cm 6.210s 228.176us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.050s 932.189us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.500s 194.441us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.170s 1138.686us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.210s 1006.146us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.210s 1006.146us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.520s 282.839us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.750s 1149.528us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.750s 1149.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 80.500s 6303.392us 1 1 100.00