Simulation Results: lc_ctrl/volatile_unlock_enabled

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.10 %
  • code
  • 83.81 %
  • assert
  • 94.13 %
  • func
  • 92.35 %
  • line
  • 97.06 %
  • branch
  • 93.62 %
  • cond
  • 79.21 %
  • toggle
  • 86.55 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.880s 140.420us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.050s 22.353us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.760s 150.636us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.480s 51.311us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 75.934us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.990s 33.060us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.760s 150.636us 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 75.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.670s 255.473us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.320s 1658.321us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.780s 13.207us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.670s 52.747us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.430s 292.087us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.150s 586.614us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 8.430s 292.087us 1 1 100.00
lc_ctrl_prog_failure 1.670s 52.747us 1 1 100.00
lc_ctrl_errors 5.150s 586.614us 1 1 100.00
lc_ctrl_security_escalation 4.700s 167.503us 1 1 100.00
lc_ctrl_jtag_state_failure 36.080s 1608.722us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.700s 1622.122us 1 1 100.00
lc_ctrl_jtag_errors 18.900s 7721.810us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 4.930s 587.863us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.580s 3443.574us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.700s 1622.122us 1 1 100.00
lc_ctrl_jtag_errors 18.900s 7721.810us 0 1 0.00
lc_ctrl_jtag_access 9.710s 2030.517us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.130s 1012.259us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.520s 565.758us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.520s 216.674us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.320s 1068.015us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.830s 187.165us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.020s 80.979us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.100s 2213.738us 1 1 100.00
lc_ctrl_jtag_alert_test 2.360s 143.411us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 12.590s 8238.319us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.010s 99.361us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 333.110s 19266.973us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.320s 275.430us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.230s 263.214us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.230s 263.214us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.050s 22.353us 1 1 100.00
lc_ctrl_csr_rw 0.760s 150.636us 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 75.934us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.250s 151.455us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.050s 22.353us 1 1 100.00
lc_ctrl_csr_rw 0.760s 150.636us 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 75.934us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.250s 151.455us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.090s 237.196us 1 1 100.00
lc_ctrl_tl_intg_err 2.680s 114.137us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.680s 114.137us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.320s 1658.321us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.430s 292.087us 1 1 100.00
lc_ctrl_sec_cm 6.090s 237.196us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.430s 292.087us 1 1 100.00
lc_ctrl_sec_cm 6.090s 237.196us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.430s 292.087us 1 1 100.00
lc_ctrl_sec_cm 6.090s 237.196us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.430s 292.087us 1 1 100.00
lc_ctrl_sec_cm 6.090s 237.196us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.430s 292.087us 1 1 100.00
lc_ctrl_sec_cm 6.090s 237.196us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.430s 292.087us 1 1 100.00
lc_ctrl_sec_cm 6.090s 237.196us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.430s 292.087us 1 1 100.00
lc_ctrl_sec_cm 6.090s 237.196us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.430s 292.087us 1 1 100.00
lc_ctrl_sec_cm 6.090s 237.196us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.700s 167.503us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.670s 255.473us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.580s 3443.574us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.940s 1579.126us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.940s 1579.126us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.290s 2189.056us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.170s 2206.669us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.170s 2206.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 26.040s 1364.720us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_jtag_errors 47308839346068069767541250554855550898677919839107162880706638933237102801336 2487
UVM_ERROR @ 7721810477 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7721810477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 94744004972539390492448981198726701915539424535185066656165317041813599878815 1092
UVM_ERROR @ 1364719663 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1364719663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---