Simulation Results: otbn

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.77 %
  • code
  • 95.21 %
  • assert
  • 89.50 %
  • func
  • 96.61 %
  • block
  • 99.37 %
  • line
  • 99.56 %
  • branch
  • 91.92 %
  • toggle
  • 91.91 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 75.136us 1 1 100.00
single_binary 1 1 100.00
otbn_single 16.000s 108.697us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 126.813us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 99.992us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 212.008us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 39.195us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 155.377us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 99.992us 1 1 100.00
otbn_csr_aliasing 4.000s 39.195us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 54.000s 1015.822us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 56.000s 13647.921us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 19.000s 135.315us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 44.000s 149.632us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 41.000s 1353.019us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 27.000s 289.969us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 7.000s 34.935us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 6.000s 64.511us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 11.000s 83.141us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 31.330us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 12.405us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 447.577us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 447.577us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 126.813us 1 1 100.00
otbn_csr_rw 3.000s 99.992us 1 1 100.00
otbn_csr_aliasing 4.000s 39.195us 1 1 100.00
otbn_same_csr_outstanding 3.000s 37.754us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 126.813us 1 1 100.00
otbn_csr_rw 3.000s 99.992us 1 1 100.00
otbn_csr_aliasing 4.000s 39.195us 1 1 100.00
otbn_same_csr_outstanding 3.000s 37.754us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 7.000s 42.201us 1 1 100.00
otbn_dmem_err 10.000s 46.038us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 10.000s 108.735us 1 1 100.00
otbn_controller_ispr_rdata_err 6.000s 36.618us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 141.059us 1 1 100.00
otbn_urnd_err 5.000s 10.774us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 7.000s 24.255us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 26.327us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 29.646us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
otbn_tl_intg_err 10.000s 159.981us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 7.000s 138.566us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 75.136us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 10.000s 46.038us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 42.201us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 159.981us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 34.935us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 42.201us 1 1 100.00
otbn_dmem_err 10.000s 46.038us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 64.511us 0 1 0.00
otbn_illegal_mem_acc 7.000s 24.255us 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 16.000s 108.697us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 42.201us 1 1 100.00
otbn_dmem_err 10.000s 46.038us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 64.511us 0 1 0.00
otbn_illegal_mem_acc 7.000s 24.255us 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 34.935us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 42.201us 1 1 100.00
otbn_dmem_err 10.000s 46.038us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 64.511us 0 1 0.00
otbn_illegal_mem_acc 7.000s 24.255us 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 16.000s 108.697us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 41.368us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 18.666us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 44.000s 350.472us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 44.000s 350.472us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 13.000s 441.915us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 73.806us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 18.000s 88.815us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 18.000s 88.815us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 8.000s 37.108us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 108.697us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 108.697us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 16.000s 108.697us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 41.000s 1353.019us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 16.000s 108.697us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 16.000s 108.697us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 22.489us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 16.000s 108.697us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 361.000s 2310.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 201.000s 1235.276us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 10.000s 35.238us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 106306347239728990489325103024619980004591794247301041243497024434940681286084 206
UVM_FATAL @ 1235275644 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1235275644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_zero_state_err_urnd 29196035471940708205733455241933188975180709406873482053687139813030450453190 109
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 64510970 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 64510970 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 64510970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 41102342985011065347063156321335520370328171767612906363443925847052250030412 96
UVM_FATAL @ 138566490 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 138566490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---