Simulation Results: otp_ctrl

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.38 %
  • code
  • 76.03 %
  • assert
  • 93.99 %
  • func
  • 68.12 %
  • line
  • 88.62 %
  • branch
  • 83.26 %
  • cond
  • 90.13 %
  • toggle
  • 75.76 %
  • FSM
  • 42.36 %
Validation stages
V1
100.00%
V2
80.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.410s 91.811us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.610s 125.422us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.160s 195.368us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.350s 561.813us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.720s 1179.107us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.610s 368.082us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.550s 200.422us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.350s 561.813us 1 1 100.00
otp_ctrl_csr_aliasing 4.610s 368.082us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.150s 84.521us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.810s 501.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 12.080s 642.987us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.260s 235.157us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 14.790s 832.349us 0 1 0.00
otp_ctrl_check_fail 5.080s 1431.172us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 2.240s 425.330us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 23.030s 866.041us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 24.350s 3036.485us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 12.290s 2273.665us 1 1 100.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 16.830s 1563.202us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.730s 76.073us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 17.840s 6019.568us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 77.020s 33376.053us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.500s 45.847us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.010s 213.930us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.080s 587.629us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.080s 587.629us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.160s 195.368us 1 1 100.00
otp_ctrl_csr_rw 1.350s 561.813us 1 1 100.00
otp_ctrl_csr_aliasing 4.610s 368.082us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.860s 431.421us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.160s 195.368us 1 1 100.00
otp_ctrl_csr_rw 1.350s 561.813us 1 1 100.00
otp_ctrl_csr_aliasing 4.610s 368.082us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.860s 431.421us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
otp_ctrl_tl_intg_err 7.650s 2603.924us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.650s 2603.924us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.610s 125.422us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.610s 125.422us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
otp_ctrl_macro_errs 2.730s 76.073us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
otp_ctrl_macro_errs 2.730s 76.073us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.470s 119.449us 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.260s 235.157us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 5.080s 1431.172us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 23.030s 866.041us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 23.030s 866.041us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 23.030s 866.041us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 23.030s 866.041us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 23.030s 866.041us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.610s 125.422us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 23.030s 866.041us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.610s 125.422us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 122.740s 11291.876us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 2.240s 425.330us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.610s 125.422us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.610s 125.422us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.730s 76.073us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.460s 6944.795us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.340s 63.172us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 78572495777172083037707332452060495446241751674495198842931132512888062078272 15043
UVM_ERROR @ 832348574 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 832348574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 37705211395723586123254625851334955294752513775825140373182171928361171758283 36295
UVM_ERROR @ 33376052727 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 33376052727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 77626257621012557610060141387634774163586419605087115506133971224142210960979 2793
UVM_ERROR @ 1431171696 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1431171696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 115266195576540957924551234310589561027864142538843906895443499875734777170047 2069
UVM_ERROR @ 76072975 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16 [0x10]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 76072975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 80883486016265215466633371344970852164625625725806310017930806964537530759197 93
UVM_ERROR @ 63172386 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 63172386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---