Simulation Results: pattgen

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.05 %
  • code
  • 98.79 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.37 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 66.367us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 27.239us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 15.800us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 1725.200us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 95.465us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 38.915us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 15.800us 1 1 100.00
pattgen_csr_aliasing 2.000s 95.465us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 437.000s 21454.917us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 17.000s 5374.076us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 57.240us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 8945.000s 1416997.239us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 37.536us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 113.787us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 1608.645us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 1608.645us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 27.239us 1 1 100.00
pattgen_csr_rw 1.000s 15.800us 1 1 100.00
pattgen_csr_aliasing 2.000s 95.465us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 88.402us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 27.239us 1 1 100.00
pattgen_csr_rw 1.000s 15.800us 1 1 100.00
pattgen_csr_aliasing 2.000s 95.465us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 88.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 348.224us 1 1 100.00
pattgen_tl_intg_err 2.000s 256.393us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 256.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 34.000s 3079.173us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 1.000s 164.960us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 70665440518770296891912583592805700945042168439029003168019518195003851927159 239
UVM_ERROR @ 1577113056 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1577128105 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1577128105 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 1577328105 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:
pattgen_stress_all 39202103175693166858542546470449104809575234342795333941049122056964729893156 167
UVM_ERROR @ 1416997238598 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
-------------------------------------
Name Type Size Value
-------------------------------------
exp_item pattgen_item - @133165