Simulation Results: pwrmgr

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.20 %
  • code
  • 89.99 %
  • assert
  • 96.08 %
  • func
  • 96.54 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 93.78 %
  • toggle
  • 89.83 %
  • FSM
  • 72.00 %
Validation stages
V1
100.00%
V2
80.00%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.670s 32.538us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.650s 36.303us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.690s 44.689us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.360s 313.212us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.810s 102.012us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.820s 41.963us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.690s 44.689us 1 1 100.00
pwrmgr_csr_aliasing 0.810s 102.012us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.810s 76.001us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.810s 76.001us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.730s 71.146us 1 1 100.00
pwrmgr_lowpower_invalid 0.700s 42.460us 1 1 100.00
reset 0 2 0.00
pwrmgr_reset 2.370s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.660s 78.671us 0 1 0.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 2.370s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.690s 44.345us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.150s 333.022us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.800s 170.361us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 5.750s 11306.488us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.620s 42.155us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.030s 54.127us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.030s 54.127us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 36.303us 1 1 100.00
pwrmgr_csr_rw 0.690s 44.689us 1 1 100.00
pwrmgr_csr_aliasing 0.810s 102.012us 1 1 100.00
pwrmgr_same_csr_outstanding 0.760s 25.298us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 36.303us 1 1 100.00
pwrmgr_csr_rw 0.690s 44.689us 1 1 100.00
pwrmgr_csr_aliasing 0.810s 102.012us 1 1 100.00
pwrmgr_same_csr_outstanding 0.760s 25.298us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.780s 28.238us 0 1 0.00
pwrmgr_tl_intg_err 0.690s 8.587us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.780s 28.238us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.780s 28.238us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.690s 8.587us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.670s 2556.264us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.690s 44.345us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.770s 123.327us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.700s 30.313us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.780s 28.238us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.780s 28.238us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.780s 28.238us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.620s 49.104us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.650s 33.061us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.870s 174.455us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 44.689us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 44.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.690s 770.388us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 4.820s 2029.654us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pwrmgr_reset 53929412680775346675627947603497345774291689131679521107214834162146503613804 152
UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
pwrmgr_escalation_timeout 57557293370519936177594117080974283169289269286702872472023609162510374074266 75
UVM_ERROR @ 770387911 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 770387911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitReleaseLcRst
pwrmgr_reset_invalid 13080267712791608974044415393852208895978485474991994770839942528789067502408 131
UVM_FATAL @ 78671132 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitReleaseLcRst
UVM_INFO @ 78671132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_sec_cm 93221005676999059636201827378923062589478515158117006639735661091850497845828 85
UVM_ERROR @ 28237592 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 28237592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 71880092476088090267868471694479298258969363228496825247591187496314800569965 85
UVM_ERROR @ 8586696 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 8586696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred!
pwrmgr_stress_all 24428439200504058847787742067125340029520702911293848806431254004522944553138 541
UVM_FATAL @ 11306488161 ps: (pwrmgr_reset_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] wait timeout occurred!
UVM_INFO @ 11306488161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---