Simulation Results: rom_ctrl/64kb

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.30 %
  • code
  • 97.97 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.07 %
  • toggle
  • 99.72 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.590s 576.367us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.330s 913.565us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.840s 701.828us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 9.850s 651.352us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 9.890s 298.556us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.300s 2355.678us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.840s 701.828us 1 1 100.00
rom_ctrl_csr_aliasing 9.890s 298.556us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 9.560s 1216.993us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.970s 1068.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.570s 1096.090us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 26.350s 768.095us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.140s 4181.064us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.360s 205.460us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.660s 216.365us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.660s 216.365us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.330s 913.565us 1 1 100.00
rom_ctrl_csr_rw 5.840s 701.828us 1 1 100.00
rom_ctrl_csr_aliasing 9.890s 298.556us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.800s 574.956us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.330s 913.565us 1 1 100.00
rom_ctrl_csr_rw 5.840s 701.828us 1 1 100.00
rom_ctrl_csr_aliasing 9.890s 298.556us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.800s 574.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.080s 6828.894us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.580s 2775.503us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_tl_intg_err 51.210s 511.915us 1 1 100.00
rom_ctrl_sec_cm 450.380s 2698.871us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 450.380s 2698.871us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 450.380s 2698.871us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.080s 6828.894us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.080s 6828.894us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.080s 6828.894us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.080s 6828.894us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.080s 6828.894us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 450.380s 2698.871us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 450.380s 2698.871us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.590s 576.367us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.590s 576.367us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.590s 576.367us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 51.210s 511.915us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.080s 6828.894us 1 1 100.00
rom_ctrl_kmac_err_chk 14.140s 4181.064us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.080s 6828.894us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.080s 6828.894us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.080s 6828.894us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.580s 2775.503us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 450.380s 2698.871us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 114.710s 4764.588us 1 1 100.00