Simulation Results: rstmgr

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.29 %
  • code
  • 99.36 %
  • assert
  • 97.99 %
  • func
  • 94.53 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.75 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.160s 205.577us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.700s 91.040us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.700s 71.665us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.290s 279.032us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.070s 101.956us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.860s 142.025us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.700s 71.665us 1 1 100.00
rstmgr_csr_aliasing 1.070s 101.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.820s 172.791us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.720s 472.483us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.780s 83.859us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.240s 1636.177us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.240s 1636.177us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.240s 1636.177us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.240s 1636.177us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 8.950s 3033.338us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.710s 75.657us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.520s 159.454us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.520s 159.454us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.700s 91.040us 1 1 100.00
rstmgr_csr_rw 0.700s 71.665us 1 1 100.00
rstmgr_csr_aliasing 1.070s 101.956us 1 1 100.00
rstmgr_same_csr_outstanding 1.030s 123.035us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.700s 91.040us 1 1 100.00
rstmgr_csr_rw 0.700s 71.665us 1 1 100.00
rstmgr_csr_aliasing 1.070s 101.956us 1 1 100.00
rstmgr_same_csr_outstanding 1.030s 123.035us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 18.940s 17835.679us 1 1 100.00
rstmgr_tl_intg_err 1.490s 474.788us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 18.940s 17835.679us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 18.940s 17835.679us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.490s 474.788us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.980s 188.039us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.840s 1951.723us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.040s 301.697us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 18.940s 17835.679us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.700s 71.665us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.700s 71.665us 1 1 100.00