Simulation Results: rv_timer

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.86 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 96.76 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.850s 34.126us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.770s 37.813us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.670s 51.311us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.830s 64.388us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.620s 76.595us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.760s 17.656us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.670s 51.311us 1 1 100.00
rv_timer_csr_aliasing 0.620s 76.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.830s 73.769us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.680s 937.045us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 366.390s 801449.139us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 366.390s 801449.139us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.990s 978.372us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.640s 14.049us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.770s 28.656us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.580s 78.864us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.580s 78.864us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.770s 37.813us 1 1 100.00
rv_timer_csr_rw 0.670s 51.311us 1 1 100.00
rv_timer_csr_aliasing 0.620s 76.595us 1 1 100.00
rv_timer_same_csr_outstanding 0.610s 17.162us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.770s 37.813us 1 1 100.00
rv_timer_csr_rw 0.670s 51.311us 1 1 100.00
rv_timer_csr_aliasing 0.620s 76.595us 1 1 100.00
rv_timer_same_csr_outstanding 0.610s 17.162us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.900s 316.711us 1 1 100.00
rv_timer_tl_intg_err 1.230s 612.947us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.230s 612.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.820s 110.154us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.550s 250.068us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 26.220s 15461.747us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 80384523255439171471369157906210450822698903485968299210179074234750041254775 77
UVM_FATAL @ 110153943 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1c6c2b04) == 0x1
UVM_INFO @ 110153943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 55660331898835391173541098421448856462832312114558659198150989928331403821223 75
UVM_FATAL @ 73769378 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x885c6f04) == 0x1
UVM_INFO @ 73769378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 109461895098017250170130035286309642886690269125357214715258526910724635985659 75
UVM_ERROR @ 250068097 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 250068097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---