Simulation Results

Simulation Results: spi_device/1r1w

30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
83.78 %

code
93.20 %

assert
87.66 %

func
70.49 %

line
99.05 %

branch
98.27 %

cond
96.12 %

toggle
83.19 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		92.31%
V2S		100.00%
unmapped		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	25.430s	3590.596us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	0.840s	74.248us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	1.150s	23.266us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	14.690s	358.111us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	14.010s	313.943us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	2.080s	42.966us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	1.150s	23.266us	1	1	100.00
	spi_device_csr_aliasing	14.010s	313.943us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	0.650s	38.104us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	1.730s	238.605us	1	1	100.00

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	0.900s	22.751us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	0.910s	0.967us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	0.890s	5.927us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	0.960s	120.063us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	0.960s	120.063us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	5.550s	5598.561us	1	1	100.00
	spi_device_tpm_sts_read	0.920s	254.337us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	4.360s	650.043us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	15.150s	30692.287us	1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	11.120s	26065.728us	1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	11.120s	26065.728us	1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	2.680s	490.125us	1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	2.680s	490.125us	1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	2.680s	490.125us	1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	2.680s	490.125us	1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	2.680s	490.125us	1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	2.140s	115.925us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	78.070s	25948.356us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	78.070s	25948.356us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	78.070s	25948.356us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	33.120s	17597.806us	1	1	100.00
	spi_device_read_buffer_direct	4.970s	875.742us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	78.070s	25948.356us	1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	69.530s	24530.085us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	1.940s	118.796us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	1.940s	118.796us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	25.430s	3590.596us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	340.270s	64170.045us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	664.190s	1278423.436us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	0.940s	15.023us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	0.640s	37.552us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	3.200s	260.580us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	3.200s	260.580us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	0.840s	74.248us	1	1	100.00
	spi_device_csr_rw	1.150s	23.266us	1	1	100.00
	spi_device_csr_aliasing	14.010s	313.943us	1	1	100.00
	spi_device_same_csr_outstanding	2.130s	520.212us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	0.840s	74.248us	1	1	100.00
	spi_device_csr_rw	1.150s	23.266us	1	1	100.00
	spi_device_csr_aliasing	14.010s	313.943us	1	1	100.00
	spi_device_same_csr_outstanding	2.130s	520.212us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	8.260s	203.966us	1	1	100.00
	spi_device_sec_cm	1.420s	397.241us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	8.260s	203.966us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	0.990s	14.228us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
	spi_device_mem_parity	108576664759119904383709822620257590496302480992797261660444100523924615714472	76	UVM_ERROR @ 779241 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[74]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM_ERROR @ 779241 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) UVM_ERROR @ 779241 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[970]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	24666752793903269240312427365481447751759563306036310960009164470065142879801	76	UVM_ERROR @ 3609278 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa53a3a [101001010011101000111010] vs 0x0 [0]) UVM_ERROR @ 3633278 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcfc55b [110011111100010101011011] vs 0x0 [0]) UVM_ERROR @ 3708278 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x22d5f0 [1000101101010111110000] vs 0x0 [0]) UVM_ERROR @ 3784278 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x221279 [1000100001001001111001] vs 0x0 [0]) UVM_ERROR @ 3829278 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x46354f [10001100011010101001111] vs 0x0 [0])