Simulation Results: spi_device/2p

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.19 %
  • code
  • 94.04 %
  • assert
  • 94.62 %
  • func
  • 72.92 %
  • line
  • 99.14 %
  • branch
  • 98.42 %
  • cond
  • 95.73 %
  • toggle
  • 87.57 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 102.020s 9945.194us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.880s 43.131us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.900s 586.113us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 27.290s 5504.784us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 8.860s 213.516us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.230s 333.163us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.900s 586.113us 1 1 100.00
spi_device_csr_aliasing 8.860s 213.516us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.650s 16.864us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.100s 122.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.160s 29.707us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.350s 27.454us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.040s 15.993us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.310s 291.375us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.310s 291.375us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 13.290s 26356.203us 1 1 100.00
spi_device_tpm_sts_read 1.020s 71.720us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 3.890s 1857.034us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.930s 91.303us 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.180s 1847.909us 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.180s 1847.909us 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.400s 2083.765us 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.400s 2083.765us 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.400s 2083.765us 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.400s 2083.765us 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.400s 2083.765us 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.320s 2998.530us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.810s 2249.388us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.810s 2249.388us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.810s 2249.388us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.010s 297.497us 1 1 100.00
spi_device_read_buffer_direct 9.040s 6118.373us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.810s 2249.388us 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 28.340s 13309.590us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.500s 184.190us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.500s 184.190us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 102.020s 9945.194us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 91.110s 17385.357us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 478.930s 75630.912us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.860s 16.262us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.680s 58.464us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.650s 306.403us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.650s 306.403us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.880s 43.131us 1 1 100.00
spi_device_csr_rw 1.900s 586.113us 1 1 100.00
spi_device_csr_aliasing 8.860s 213.516us 1 1 100.00
spi_device_same_csr_outstanding 2.650s 146.270us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.880s 43.131us 1 1 100.00
spi_device_csr_rw 1.900s 586.113us 1 1 100.00
spi_device_csr_aliasing 8.860s 213.516us 1 1 100.00
spi_device_same_csr_outstanding 2.650s 146.270us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 16.870s 1344.205us 1 1 100.00
spi_device_sec_cm 1.010s 99.581us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 16.870s 1344.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 128.690s 176664.724us 1 1 100.00