Simulation Results: sram_ctrl/main

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.18 %
  • code
  • 91.36 %
  • assert
  • 95.83 %
  • func
  • 95.36 %
  • line
  • 97.94 %
  • branch
  • 95.54 %
  • cond
  • 91.68 %
  • toggle
  • 90.71 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 38.140s 3151.895us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.720s 38.262us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.650s 55.614us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.520s 42.397us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 21.051us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.340s 362.643us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.650s 55.614us 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 21.051us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 116.530s 20915.852us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 50.920s 1446.902us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 206.840s 9310.525us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 156.870s 13486.665us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1697.190s 144547.581us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 600.630s 81434.152us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 23.810s 11465.102us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 124.740s 7836.658us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 11.850s 1847.533us 1 1 100.00
sram_ctrl_partial_access_b2b 316.560s 61979.831us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 23.780s 1329.823us 1 1 100.00
sram_ctrl_throughput_w_partial_write 67.580s 786.218us 1 1 100.00
sram_ctrl_throughput_w_readback 29.280s 3490.499us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 533.050s 7285.533us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.700s 360.596us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 4268.010s 239789.928us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.810s 44.603us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.870s 110.170us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.870s 110.170us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.720s 38.262us 1 1 100.00
sram_ctrl_csr_rw 0.650s 55.614us 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 21.051us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 34.211us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.720s 38.262us 1 1 100.00
sram_ctrl_csr_rw 0.650s 55.614us 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 21.051us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 34.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.990s 14777.933us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.760s 442.841us 1 1 100.00
sram_ctrl_sec_cm 0.730s 1.781us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.730s 1.781us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.760s 442.841us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 533.050s 7285.533us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 533.050s 7285.533us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.650s 55.614us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 124.740s 7836.658us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 124.740s 7836.658us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 124.740s 7836.658us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 23.810s 11465.102us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.300s 1326.729us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.990s 14777.933us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.690s 3193.410us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 38.140s 3151.895us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 38.140s 3151.895us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 124.740s 7836.658us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.730s 1.781us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 23.810s 11465.102us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.730s 1.781us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.730s 1.781us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 38.140s 3151.895us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.730s 1.781us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 13.610s 5577.273us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 5119289822532543733583030914756692500718712073065919576309690621353349986783 99
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 1781395 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 1781395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---