Simulation Results: sram_ctrl/ret

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.38 %
  • code
  • 89.46 %
  • assert
  • 95.51 %
  • func
  • 95.18 %
  • line
  • 97.49 %
  • branch
  • 95.20 %
  • cond
  • 92.53 %
  • toggle
  • 90.66 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 10.240s 598.660us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.930s 56.337us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.640s 30.137us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.730s 298.293us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 69.893us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.040s 53.477us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.640s 30.137us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 69.893us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.210s 96.143us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.170s 879.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 306.520s 27686.652us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 196.660s 2825.814us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 61.730s 5385.141us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 573.080s 11001.833us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 8.430s 1138.399us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 219.670s 7854.285us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 62.030s 409.244us 1 1 100.00
sram_ctrl_partial_access_b2b 267.330s 72314.564us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 31.070s 118.083us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.800s 128.706us 1 1 100.00
sram_ctrl_throughput_w_readback 45.040s 260.494us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 546.970s 4779.869us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.910s 33.715us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1052.330s 119392.666us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.760s 30.054us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.600s 126.864us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.600s 126.864us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.930s 56.337us 1 1 100.00
sram_ctrl_csr_rw 0.640s 30.137us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 69.893us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.740s 17.813us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.930s 56.337us 1 1 100.00
sram_ctrl_csr_rw 0.640s 30.137us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 69.893us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.740s 17.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.620s 1670.551us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.920s 3.524us 0 1 0.00
sram_ctrl_tl_intg_err 1.910s 319.283us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.920s 3.524us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.910s 319.283us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 546.970s 4779.869us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 546.970s 4779.869us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.640s 30.137us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 219.670s 7854.285us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 219.670s 7854.285us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 219.670s 7854.285us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 8.430s 1138.399us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.070s 366.437us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.620s 1670.551us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.370s 30.226us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 10.240s 598.660us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 10.240s 598.660us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 219.670s 7854.285us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.920s 3.524us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 8.430s 1138.399us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.920s 3.524us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.920s 3.524us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 10.240s 598.660us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.920s 3.524us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 321.110s 11485.416us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 45443913632728570873264983051978352058489262036825114062523912426399135159159 100
UVM_ERROR @ 3524284 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3524284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---