Simulation Results: sysrst_ctrl

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.14 %
  • code
  • 92.39 %
  • assert
  • 93.49 %
  • func
  • 60.55 %
  • line
  • 97.17 %
  • branch
  • 97.33 %
  • cond
  • 94.39 %
  • toggle
  • 100.00 %
  • FSM
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.540s 2132.209us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.200s 2449.455us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 0.990s 2261.671us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.590s 2551.569us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.210s 6081.792us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.590s 2122.004us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 133.750s 75220.283us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.670s 2458.069us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.890s 2168.798us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.590s 2122.004us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.670s 2458.069us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 19.880s 118253.058us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 198.950s 109897.471us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 95.140s 248601.106us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.670s 3989.467us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.660s 2512.463us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.370s 2063.776us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.350s 2789.702us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.500s 2631.417us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.640s 3804.366us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 65.540s 37066.663us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 1.580s 7825.870us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.740s 2026.905us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.050s 2015.671us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.760s 2034.911us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.760s 2034.911us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.210s 6081.792us 1 1 100.00
sysrst_ctrl_csr_rw 1.590s 2122.004us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.670s 2458.069us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.240s 10030.923us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.210s 6081.792us 1 1 100.00
sysrst_ctrl_csr_rw 1.590s 2122.004us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.670s 2458.069us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.240s 10030.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 10.920s 22079.018us 1 1 100.00
sysrst_ctrl_tl_intg_err 39.970s 22243.345us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 39.970s 22243.345us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 3.920s 7053.802us 1 1 100.00