Simulation Results: uart

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.01 %
  • code
  • 95.76 %
  • assert
  • 97.12 %
  • func
  • 53.15 %
  • line
  • 99.06 %
  • branch
  • 96.97 %
  • cond
  • 95.45 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 17.200s 6219.631us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.680s 37.670us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.620s 82.439us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.870s 112.790us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.900s 31.897us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.070s 121.610us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.620s 82.439us 1 1 100.00
uart_csr_aliasing 0.900s 31.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 146.300s 88155.564us 1 1 100.00
parity 2 2 100.00
uart_smoke 17.200s 6219.631us 1 1 100.00
uart_tx_rx 146.300s 88155.564us 1 1 100.00
parity_error 2 2 100.00
uart_intr 20.040s 39077.665us 1 1 100.00
uart_rx_parity_err 115.980s 111384.553us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 146.300s 88155.564us 1 1 100.00
uart_intr 20.040s 39077.665us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 24.650s 37692.876us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 27.800s 85222.631us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 96.850s 92787.108us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 20.040s 39077.665us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 20.040s 39077.665us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 20.040s 39077.665us 1 1 100.00
perf 1 1 100.00
uart_perf 476.710s 13467.494us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.660s 1524.663us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.660s 1524.663us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 20.670s 47366.895us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 7.340s 26351.036us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.450s 1448.256us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 29.150s 4857.226us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 133.680s 99093.041us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 4.800s 9364.376us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.710s 48.802us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.740s 13.100us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.040s 33.668us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.040s 33.668us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.680s 37.670us 1 1 100.00
uart_csr_rw 0.620s 82.439us 1 1 100.00
uart_csr_aliasing 0.900s 31.897us 1 1 100.00
uart_same_csr_outstanding 0.620s 43.173us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.680s 37.670us 1 1 100.00
uart_csr_rw 0.620s 82.439us 1 1 100.00
uart_csr_aliasing 0.900s 31.897us 1 1 100.00
uart_same_csr_outstanding 0.620s 43.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 0.860s 46.976us 1 1 100.00
uart_sec_cm 1.080s 65.308us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.860s 46.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 59.810s 4830.871us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 17862402967385499119937227234936998073577314900877890031186955642086248521249 79
UVM_ERROR @ 34483056207 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 34483093244 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 34483241392 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (196 [0xc4] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 35340425720 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 35340425720 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr
uart_stress_all 80809924704417074605978057767522923003274679577861398262284194251722032495877 75
UVM_ERROR @ 177281264 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 177281264 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 177281264 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 177281264 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
UVM_ERROR @ 420437437 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0