Simulation Results: adc_ctrl

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 69.97 %
  • code
  • 96.79 %
  • assert
  • 95.62 %
  • func
  • 17.49 %
  • line
  • 99.02 %
  • branch
  • 97.65 %
  • cond
  • 92.68 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.700s 5742.961us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.050s 748.719us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.930s 445.868us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 31.510s 26406.062us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.520s 747.376us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.860s 521.216us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.930s 445.868us 1 1 100.00
adc_ctrl_csr_aliasing 1.520s 747.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 297.720s 165451.405us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 565.770s 327825.950us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 139.270s 333818.194us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 191.350s 160481.324us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 561.760s 405402.976us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 196.970s 207766.457us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 114.220s 161384.326us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 86.150s 189493.844us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 9.720s 5094.953us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 20.160s 23105.662us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 145.880s 86434.662us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 128.070s 326092.797us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.180s 514.329us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.920s 368.708us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.370s 333.546us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.370s 333.546us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.050s 748.719us 1 1 100.00
adc_ctrl_csr_rw 0.930s 445.868us 1 1 100.00
adc_ctrl_csr_aliasing 1.520s 747.376us 1 1 100.00
adc_ctrl_same_csr_outstanding 10.980s 4296.793us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.050s 748.719us 1 1 100.00
adc_ctrl_csr_rw 0.930s 445.868us 1 1 100.00
adc_ctrl_csr_aliasing 1.520s 747.376us 1 1 100.00
adc_ctrl_same_csr_outstanding 10.980s 4296.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 3.330s 4432.390us 1 1 100.00
adc_ctrl_sec_cm 2.500s 4568.469us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 3.330s 4432.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 4.780s 2514.639us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_stress_all 4243114417906752459363351564203050587788696255618349871036324731483120335645 363
UVM_ERROR @ 326092796969 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 326092796969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---