| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 2.000s | 123.300us | 1 | 1 | 100.00 | |
| smoke | 1 | 1 | 100.00 | |||
| aes_smoke | 3.000s | 119.163us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 91.511us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aes_csr_rw | 1.000s | 65.384us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aes_csr_bit_bash | 4.000s | 1037.528us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aes_csr_aliasing | 4.000s | 133.092us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 2.000s | 80.130us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aes_csr_rw | 1.000s | 65.384us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 4.000s | 133.092us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 3 | 3 | 100.00 | |||
| aes_smoke | 3.000s | 119.163us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 298.979us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| key_length | 3 | 3 | 100.00 | |||
| aes_smoke | 3.000s | 119.163us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 298.979us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| back2back | 2 | 2 | 100.00 | |||
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| aes_b2b | 5.000s | 229.701us | 1 | 1 | 100.00 | |
| backpressure | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| multi_message | 4 | 4 | 100.00 | |||
| aes_smoke | 3.000s | 119.163us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 298.979us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| aes_alert_reset | 3.000s | 273.787us | 1 | 1 | 100.00 | |
| failure_test | 3 | 3 | 100.00 | |||
| aes_man_cfg_err | 2.000s | 57.769us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 298.979us | 1 | 1 | 100.00 | |
| aes_alert_reset | 3.000s | 273.787us | 1 | 1 | 100.00 | |
| trigger_clear_test | 1 | 1 | 100.00 | |||
| aes_clear | 4.000s | 103.035us | 1 | 1 | 100.00 | |
| nist_test_vectors | 1 | 1 | 100.00 | |||
| aes_nist_vectors | 9.000s | 879.707us | 1 | 1 | 100.00 | |
| nist_test_vectors_gcm | 1 | 1 | 100.00 | |||
| aes_nist_vectors_gcm | 7.000s | 1384.688us | 1 | 1 | 100.00 | |
| reset_recovery | 1 | 1 | 100.00 | |||
| aes_alert_reset | 3.000s | 273.787us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| sideload | 2 | 2 | 100.00 | |||
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| aes_sideload | 5.000s | 139.266us | 1 | 1 | 100.00 | |
| deinitialization | 1 | 1 | 100.00 | |||
| aes_deinit | 3.000s | 66.990us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| aes_stress_all | 18.000s | 1487.884us | 1 | 1 | 100.00 | |
| gcm_save_and_restore | 1 | 1 | 100.00 | |||
| aes_gcm_save_restore | 3.000s | 152.769us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aes_alert_test | 2.000s | 209.317us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 2.000s | 108.795us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 2.000s | 108.795us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 91.511us | 1 | 1 | 100.00 | |
| aes_csr_rw | 1.000s | 65.384us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 4.000s | 133.092us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 3.000s | 193.183us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 91.511us | 1 | 1 | 100.00 | |
| aes_csr_rw | 1.000s | 65.384us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 4.000s | 133.092us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 3.000s | 193.183us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 1 | 1 | 100.00 | |||
| aes_reseed | 4.000s | 126.255us | 1 | 1 | 100.00 | |
| fault_inject | 3 | 3 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| aes_control_fi | 2.000s | 54.703us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 56.682us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 274.170us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 274.170us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 274.170us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 274.170us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 3.000s | 127.235us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| aes_sec_cm | 6.000s | 1980.779us | 1 | 1 | 100.00 | |
| aes_tl_intg_err | 2.000s | 226.016us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aes_tl_intg_err | 2.000s | 226.016us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| aes_alert_reset | 3.000s | 273.787us | 1 | 1 | 100.00 | |
| sec_cm_main_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 274.170us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 274.170us | 1 | 1 | 100.00 | |
| sec_cm_main_config_sparse | 4 | 4 | 100.00 | |||
| aes_smoke | 3.000s | 119.163us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| aes_alert_reset | 3.000s | 273.787us | 1 | 1 | 100.00 | |
| aes_core_fi | 4.000s | 446.765us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_sparse | 4 | 4 | 100.00 | |||
| aes_gcm_save_restore | 3.000s | 152.769us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 298.979us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| aes_core_fi | 4.000s | 446.765us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 274.170us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_regwen | 2 | 2 | 100.00 | |||
| aes_readability | 3.000s | 71.173us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 2 | 2 | 100.00 | |||
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| aes_sideload | 5.000s | 139.266us | 1 | 1 | 100.00 | |
| sec_cm_key_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 3.000s | 71.173us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 3.000s | 71.173us | 1 | 1 | 100.00 | |
| sec_cm_key_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 3.000s | 71.173us | 1 | 1 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 3.000s | 71.173us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 3.000s | 71.173us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_key_sca | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| sec_cm_key_masking | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 142.984us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 1 | 1 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_redun | 4 | 4 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| aes_control_fi | 2.000s | 54.703us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 56.682us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 111.969us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_sparse | 1 | 1 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_redun | 3 | 3 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| aes_control_fi | 2.000s | 54.703us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 56.682us | 1 | 1 | 100.00 | |
| sec_cm_cipher_ctr_redun | 1 | 1 | 100.00 | |||
| aes_cipher_fi | 2.000s | 56.682us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_sparse | 1 | 1 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_redun | 3 | 3 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| aes_control_fi | 2.000s | 54.703us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 111.969us | 1 | 1 | 100.00 | |
| sec_cm_ghash_fsm_sparse | 1 | 1 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_sparse | 4 | 4 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| aes_control_fi | 2.000s | 54.703us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 56.682us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 111.969us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| aes_alert_reset | 3.000s | 273.787us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 4 | 4 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| aes_control_fi | 2.000s | 54.703us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 56.682us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 111.969us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_local_esc | 4 | 4 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| aes_control_fi | 2.000s | 54.703us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 56.682us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 111.969us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_local_esc | 3 | 3 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| aes_control_fi | 2.000s | 54.703us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 111.969us | 1 | 1 | 100.00 | |
| sec_cm_ghash_fsm_local_esc | 2 | 2 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| aes_ghash_fi | 2.000s | 67.397us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_local_esc | 3 | 3 | 100.00 | |||
| aes_fi | 4.000s | 91.615us | 1 | 1 | 100.00 | |
| aes_control_fi | 2.000s | 54.703us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 56.682us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| aes_stress_all_with_rand_reset | 19.000s | 817.969us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| aes_stress_all_with_rand_reset | 2735224854395181096734296738506525832284095728787487224909642466385405361081 | 679 |
UVM_ERROR @ 817969312 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 817969312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|