Simulation Results: chip

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.39 %
  • code
  • 84.48 %
  • assert
  • 97.50 %
  • func
  • 29.20 %
  • line
  • 93.89 %
  • branch
  • 92.33 %
  • cond
  • 87.75 %
  • toggle
  • 91.29 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
83.45%
V2S
100.00%
V3
61.54%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 118.520s 2278.925us 1 1 100.00
chip_sw_example_rom 61.970s 2351.526us 1 1 100.00
chip_sw_example_manufacturer 164.350s 3024.940us 1 1 100.00
chip_sw_example_concurrency 119.090s 2262.691us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 209.090s 5947.977us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 221.100s 4870.476us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 376.540s 5802.095us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3573.780s 28785.987us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 49.400s 1951.034us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3573.780s 28785.987us 1 1 100.00
chip_csr_rw 221.100s 4870.476us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.780s 130.004us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 334.260s 4490.326us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 334.260s 4490.326us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 334.260s 4490.326us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 367.610s 4482.208us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 367.610s 4482.208us 1 1 100.00
chip_sw_uart_tx_rx_idx1 349.160s 4074.126us 1 1 100.00
chip_sw_uart_tx_rx_idx2 409.090s 4841.925us 1 1 100.00
chip_sw_uart_tx_rx_idx3 366.540s 4391.373us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1105.780s 8646.833us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 432.780s 4223.595us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 626.950s 8234.510us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 151.900s 3913.055us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 151.900s 3913.055us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 187.910s 3320.640us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 186.940s 3800.507us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 225.460s 4506.314us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 107.890s 2990.087us 1 1 100.00
chip_tap_straps_testunlock0 181.840s 3701.614us 1 1 100.00
chip_tap_straps_rma 456.540s 7337.776us 1 1 100.00
chip_tap_straps_prod 908.020s 14722.753us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 183.730s 2624.169us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 861.540s 9304.180us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 462.700s 6222.451us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 462.700s 6222.451us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 509.880s 6891.403us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1263.150s 12934.364us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 337.330s 4117.946us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 578.050s 5834.429us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3571.030s 18427.029us 1 1 100.00
chip_sw_aes_enc_jitter_en 157.040s 2579.546us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 808.930s 8474.109us 1 1 100.00
chip_sw_hmac_enc_jitter_en 157.320s 2561.019us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1051.790s 9284.675us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 193.830s 3302.189us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 414.590s 5026.995us 1 1 100.00
chip_sw_clkmgr_jitter 125.920s 3511.727us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 214.150s 3622.971us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 521.690s 6720.492us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 242.750s 5171.991us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 166.260s 2445.894us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 242.750s 5171.991us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 137.270s 3085.536us 1 1 100.00
chip_sw_aes_smoketest 172.380s 2836.514us 1 1 100.00
chip_sw_aon_timer_smoketest 175.870s 3474.780us 1 1 100.00
chip_sw_clkmgr_smoketest 119.900s 3367.433us 1 1 100.00
chip_sw_csrng_smoketest 170.690s 3422.783us 1 1 100.00
chip_sw_entropy_src_smoketest 532.380s 5394.874us 1 1 100.00
chip_sw_gpio_smoketest 160.620s 3566.398us 1 1 100.00
chip_sw_hmac_smoketest 203.470s 3530.372us 1 1 100.00
chip_sw_kmac_smoketest 210.960s 3810.859us 1 1 100.00
chip_sw_otbn_smoketest 610.350s 6028.873us 1 1 100.00
chip_sw_pwrmgr_smoketest 269.200s 5579.696us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 236.410s 4862.776us 1 1 100.00
chip_sw_rv_plic_smoketest 161.220s 3308.219us 1 1 100.00
chip_sw_rv_timer_smoketest 196.790s 3380.034us 1 1 100.00
chip_sw_rstmgr_smoketest 156.150s 2969.156us 1 1 100.00
chip_sw_sram_ctrl_smoketest 123.640s 3551.193us 1 1 100.00
chip_sw_uart_smoketest 119.030s 2142.866us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 144.010s 3101.089us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 328.710s 4535.345us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7701.330s 64985.105us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2428.180s 15200.642us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 164.760s 5527.301us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 175.660s 2999.059us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 200.150s 3016.244us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6894.120s 57171.926us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 6932.190s 58541.394us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 54.490s 2257.353us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 54.490s 2257.353us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3573.780s 28785.987us 1 1 100.00
chip_same_csr_outstanding 2908.160s 32599.581us 1 1 100.00
chip_csr_hw_reset 209.090s 5947.977us 1 1 100.00
chip_csr_rw 221.100s 4870.476us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3573.780s 28785.987us 1 1 100.00
chip_same_csr_outstanding 2908.160s 32599.581us 1 1 100.00
chip_csr_hw_reset 209.090s 5947.977us 1 1 100.00
chip_csr_rw 221.100s 4870.476us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 10.290s 402.946us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.930s 44.347us 1 1 100.00
xbar_smoke_large_delays 60.020s 9584.699us 1 1 100.00
xbar_smoke_slow_rsp 45.230s 4541.623us 1 1 100.00
xbar_random_zero_delays 13.790s 223.537us 1 1 100.00
xbar_random_large_delays 160.940s 26250.474us 1 1 100.00
xbar_random_slow_rsp 224.920s 24951.822us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 40.400s 1286.785us 1 1 100.00
xbar_error_and_unmapped_addr 22.370s 312.419us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 15.300s 426.962us 1 1 100.00
xbar_error_and_unmapped_addr 22.370s 312.419us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 25.200s 1088.814us 1 1 100.00
xbar_access_same_device_slow_rsp 153.820s 16656.782us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 43.490s 2230.159us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 317.540s 14016.041us 1 1 100.00
xbar_stress_all_with_error 17.580s 605.712us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 73.600s 352.159us 1 1 100.00
xbar_stress_all_with_reset_error 21.930s 33.072us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2428.180s 15200.642us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 1991.110s 28389.928us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2360.100s 15478.038us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2126.130s 11597.029us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2523.720s 15739.023us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2641.610s 16050.861us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2614.240s 18561.017us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2519.180s 14944.243us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 17.840s 10.340us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 17.430s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 16.300s 10.180us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 17.350s 10.180us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 20.540s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 18.230s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 16.580s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 17.410s 10.300us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 17.750s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 17.650s 10.200us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.010s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 16.350s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.500s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 15.820s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.030s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.800s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.530s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 17.660s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16.880s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 17.260s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.870s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.490s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.460s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 16.310s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.530s 10.240us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2071.830s 11822.426us 1 1 100.00
rom_e2e_asm_init_dev 2514.460s 15595.225us 1 1 100.00
rom_e2e_asm_init_prod 2487.150s 16195.845us 1 1 100.00
rom_e2e_asm_init_prod_end 2387.730s 16152.620us 1 1 100.00
rom_e2e_asm_init_rma 2335.890s 15531.891us 1 1 100.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 2385.060s 16776.257us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 4285.760s 30620.939us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 4394.910s 31094.344us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2542.790s 16316.374us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3190.340s 34537.038us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3190.340s 34537.038us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 185.670s 3050.066us 1 1 100.00
chip_sw_aes_enc_jitter_en 157.040s 2579.546us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 160.600s 2632.040us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 129.500s 2887.556us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 655.130s 6271.403us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 198.830s 2974.383us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 453.480s 5984.047us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 340.940s 4675.406us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 518.960s 5387.489us 1 1 100.00
chip_plic_all_irqs_10 266.090s 3798.198us 1 1 100.00
chip_plic_all_irqs_20 371.730s 4288.480us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 167.270s 3399.020us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 971.720s 14153.079us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 296.650s 4734.044us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 109.650s 2720.105us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 848.280s 6816.097us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1011.730s 7548.262us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 822.770s 8169.915us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7134.860s 256631.054us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 281.290s 3963.585us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 269.200s 5579.696us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 281.290s 3963.585us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 423.470s 7658.827us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 423.470s 7658.827us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 351.660s 7723.054us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 412.250s 5265.364us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 566.830s 6243.020us 1 1 100.00
chip_sw_aes_idle 129.500s 2887.556us 1 1 100.00
chip_sw_hmac_enc_idle 202.530s 2615.857us 1 1 100.00
chip_sw_kmac_idle 152.610s 2469.798us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 304.400s 5792.546us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 355.710s 5319.147us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 249.730s 4771.652us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 312.510s 4119.571us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 753.220s 10852.856us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 414.740s 4856.761us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 397.460s 4868.303us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 346.960s 3986.299us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 351.930s 4115.440us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 368.040s 3631.635us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 359.490s 4838.469us 1 1 100.00
chip_sw_ast_clk_outputs 509.880s 6891.403us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 625.930s 14115.987us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 346.960s 3986.299us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 351.930s 4115.440us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 337.330s 4117.946us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 578.050s 5834.429us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3571.030s 18427.029us 1 1 100.00
chip_sw_aes_enc_jitter_en 157.040s 2579.546us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 808.930s 8474.109us 1 1 100.00
chip_sw_hmac_enc_jitter_en 157.320s 2561.019us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1051.790s 9284.675us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 193.830s 3302.189us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 414.590s 5026.995us 1 1 100.00
chip_sw_clkmgr_jitter 125.920s 3511.727us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 120.990s 2739.351us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 416.820s 5013.373us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 692.240s 7705.878us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3101.580s 24621.669us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 151.710s 3224.364us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 175.780s 3035.080us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 798.150s 8615.519us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 179.680s 3550.088us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 341.170s 4216.010us 1 1 100.00
chip_sw_flash_init_reduced_freq 1174.790s 20713.470us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 7089.180s 86866.718us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 509.880s 6891.403us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 316.280s 4876.893us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 223.300s 3095.517us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 340.940s 4675.406us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 848.280s 6816.097us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 922.770s 6614.730us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 343.190s 5586.175us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 542.430s 7462.242us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 170.800s 3197.181us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3654.930s 22663.983us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 129.050s 2914.036us 1 1 100.00
chip_sw_edn_entropy_reqs 615.960s 6607.987us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 129.050s 2914.036us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 922.770s 6614.730us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 186.260s 2752.362us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1406.120s 21872.138us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 605.350s 5090.235us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 578.050s 5834.429us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 411.770s 3552.295us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 337.330s 4117.946us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3678.750s 44128.753us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1406.120s 21872.138us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 235.930s 3118.866us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 941.570s 8202.020us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 211.070s 3702.423us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3678.750s 44128.753us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 211.070s 3702.423us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 211.070s 3702.423us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 211.070s 3702.423us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 211.070s 3702.423us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 340.940s 4675.406us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 104.100s 4265.006us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 536.790s 5630.749us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 428.560s 6344.928us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 428.560s 6344.928us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 148.440s 2953.521us 1 1 100.00
chip_sw_hmac_enc_jitter_en 157.320s 2561.019us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 202.530s 2615.857us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1344.670s 10832.733us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 633.930s 5709.285us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 407.450s 5453.990us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 344.860s 3849.922us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 397.890s 5063.230us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 257.930s 3826.295us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 941.570s 8202.020us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1051.790s 9284.675us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 783.620s 8470.797us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 655.130s 6271.403us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2795.080s 16062.387us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 178.950s 3747.923us 1 1 100.00
chip_sw_kmac_mode_kmac 208.960s 3886.636us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 193.830s 3302.189us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 941.570s 8202.020us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 581.400s 11592.955us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 125.780s 2619.057us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1249.130s 9572.119us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 152.610s 2469.798us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 453.480s 5984.047us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 107.890s 2990.087us 1 1 100.00
chip_tap_straps_rma 456.540s 7337.776us 1 1 100.00
chip_tap_straps_prod 908.020s 14722.753us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 156.330s 2958.714us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 581.400s 11592.955us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 581.400s 11592.955us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 581.400s 11592.955us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 705.140s 7210.859us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_prim_tl_access 104.100s 4265.006us 1 1 100.00
chip_rv_dm_lc_disabled 677.010s 20583.013us 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 211.070s 3702.423us 0 1 0.00
chip_sw_flash_rma_unlocked 3678.750s 44128.753us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 182.070s 3098.306us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 458.710s 6276.533us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 558.560s 7580.050us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 498.960s 7015.834us 0 1 0.00
chip_sw_lc_ctrl_transition 581.400s 11592.955us 1 1 100.00
chip_sw_keymgr_key_derivation 941.570s 8202.020us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 334.800s 9140.139us 1 1 100.00
chip_sw_sram_ctrl_execution_main 450.880s 8640.279us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 625.930s 14115.987us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 414.740s 4856.761us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 397.460s 4868.303us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 346.960s 3986.299us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 351.930s 4115.440us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 368.040s 3631.635us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 359.490s 4838.469us 1 1 100.00
chip_tap_straps_dev 107.890s 2990.087us 1 1 100.00
chip_tap_straps_rma 456.540s 7337.776us 1 1 100.00
chip_tap_straps_prod 908.020s 14722.753us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 134.530s 3527.369us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 103.210s 3723.907us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 78.250s 3441.445us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 91.160s 2696.970us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_rv_dm_lc_disabled 677.010s 20583.013us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1446.660s 28887.446us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 633.240s 11221.004us 0 1 0.00
chip_sw_lc_walkthrough_prod 711.160s 12291.980us 0 1 0.00
chip_sw_lc_walkthrough_prodend 546.270s 11107.485us 1 1 100.00
chip_sw_lc_walkthrough_rma 399.320s 6443.193us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1446.660s 28887.446us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 59.940s 1924.387us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 59.880s 2625.889us 1 1 100.00
rom_volatile_raw_unlock 59.510s 2606.495us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3446.630s 16960.103us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3571.030s 18427.029us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 566.830s 6243.020us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 566.830s 6243.020us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 566.830s 6243.020us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 279.790s 3710.639us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 581.400s 11592.955us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1406.120s 21872.138us 1 1 100.00
chip_sw_otbn_mem_scramble 279.790s 3710.639us 1 1 100.00
chip_sw_keymgr_key_derivation 941.570s 8202.020us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 343.560s 4701.422us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 152.440s 3013.742us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1406.120s 21872.138us 1 1 100.00
chip_sw_otbn_mem_scramble 279.790s 3710.639us 1 1 100.00
chip_sw_keymgr_key_derivation 941.570s 8202.020us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 343.560s 4701.422us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 152.440s 3013.742us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 581.400s 11592.955us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 360.720s 5719.991us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 156.330s 2958.714us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 104.100s 4265.006us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 182.070s 3098.306us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 458.710s 6276.533us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 558.560s 7580.050us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 498.960s 7015.834us 0 1 0.00
chip_sw_lc_ctrl_transition 581.400s 11592.955us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 104.100s 4265.006us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 764.040s 7366.062us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 276.100s 6785.230us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 967.910s 26680.855us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 202.600s 7400.342us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 371.820s 8046.199us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 517.830s 6679.013us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 972.450s 21986.136us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 187.010s 5820.892us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 423.470s 7658.827us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 667.990s 9810.843us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 405.680s 5557.839us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 276.100s 6785.230us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 322.900s 5009.408us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2183.250s 26499.896us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 297.720s 5850.964us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 339.660s 6839.537us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1565.630s 21706.177us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 725.710s 7554.744us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1059.140s 10975.133us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1538.950s 26208.890us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 163.940s 2902.856us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 340.940s 4675.406us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 334.800s 9140.139us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 334.800s 9140.139us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 1059.140s 10975.133us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1565.630s 21706.177us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 405.680s 5557.839us 1 1 100.00
chip_sw_pwrmgr_smoketest 269.200s 5579.696us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 251.470s 4548.663us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 244.010s 3569.139us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 222.210s 4047.451us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 971.720s 14153.079us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 142.750s 2890.184us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 340.940s 4675.406us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1011.730s 7548.262us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 491.540s 4858.255us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 469.350s 4582.432us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 209.160s 2947.381us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 152.440s 3013.742us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 244.010s 3569.139us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 244.010s 3569.139us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 549.730s 8719.667us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 937.320s 13758.073us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 251.470s 4548.663us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 188.520s 3704.638us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 289.900s 6584.404us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 456.540s 7337.776us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 677.010s 20583.013us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 518.960s 5387.489us 1 1 100.00
chip_plic_all_irqs_10 266.090s 3798.198us 1 1 100.00
chip_plic_all_irqs_20 371.730s 4288.480us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 194.680s 2882.167us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 125.360s 3327.513us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2428.180s 15200.642us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 516.660s 7431.975us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 212.270s 3417.792us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 235.630s 3884.347us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 170.420s 3317.172us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 343.560s 4701.422us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 414.590s 5026.995us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 348.360s 7769.047us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 421.020s 8308.118us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 450.880s 8640.279us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 340.940s 4675.406us 1 1 100.00
chip_sw_data_integrity_escalation 462.700s 6222.451us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 725.710s 7554.744us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1064.430s 23938.013us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 156.210s 2981.600us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 191.540s 4171.559us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 331.810s 4237.258us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1064.430s 23938.013us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1064.430s 23938.013us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2406.370s 20618.985us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2406.370s 20618.985us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 341.520s 5435.096us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3190.340s 34537.038us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 125.210s 3048.226us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 136.340s 2603.242us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 277.040s 4000.287us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 332.340s 4138.086us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1061.380s 8542.875us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4864.360s 31381.865us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1828.840s 12346.221us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 158.230s 3478.464us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 226.770s 3587.667us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 166.670s 3307.044us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 8683.880s 72214.313us 1 1 100.00
chip_sw_power_max_load 0 1 0.00
chip_sw_power_virus 194.450s 2300.566us 0 1 0.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 443.560s 6477.632us 0 1 0.00
rom_e2e_jtag_debug_dev 173.480s 4314.505us 0 1 0.00
rom_e2e_jtag_debug_rma 408.250s 6160.213us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 81.780s 3109.903us 0 1 0.00
rom_e2e_jtag_inject_dev 69.170s 2780.065us 0 1 0.00
rom_e2e_jtag_inject_rma 59.540s 2059.451us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 8.043s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 234.520s 3292.152us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 295.940s 2783.843us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 522.870s 4170.111us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 822.600s 6557.552us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 256.020s 2925.609us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 635.790s 5873.721us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 142.610s 2867.463us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 182.250s 3673.773us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 328.810s 6858.624us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 317.980s 5903.322us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1059.140s 10975.133us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 443.560s 6477.632us 0 1 0.00
rom_e2e_jtag_debug_dev 173.480s 4314.505us 0 1 0.00
rom_e2e_jtag_debug_rma 408.250s 6160.213us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 320.690s 6053.984us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 340.940s 4675.406us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 4972.130s 38641.343us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 4972.130s 38641.343us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 207.400s 3882.848us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 367.610s 4482.208us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3090.600s 19180.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 203.980s 3472.664us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 451.840s 5652.099us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.480s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 114.420s 2953.646us 1 1 100.00
chip_sw_otp_ctrl_descrambling 184.160s 3118.305us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 240.280s 4274.911us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.810s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 165.600s 2864.585us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 107649428533809497397360184973732846861576544166062530658323017869619562288427 217
UVM_ERROR @ 2257.352912 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31791) { a_addr: 'h10360 a_data: 'h9d13dc22 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h1bab5 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2257.352912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 58264780969531561415913629090904559531810464481712989724366345526908299558490 224
UVM_ERROR @ 1951.034098 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31729) { a_addr: 'h104bc a_data: 'hf17aebd4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1a a_opcode: 'h4 a_user: 'h18107 d_param: 'h0 d_source: 'h1a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1951.034098 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 4582305654851211565432052342217321422874752037006826239962745885877023724000 333
UVM_ERROR @ 3569.138588 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@108463) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 3569.138588 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 9062882166615533640046989679234249699610442096315600812408723906193739796756 451
UVM_ERROR @ 3320.640000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 3320.640000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 113355833405836554151460905283999366896527516997452688876228207500649519374778 320
UVM_ERROR @ 3417.792037 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3417.792037 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 92757981459867716449106109998113835427752358030151522133708558386329099313233 309
UVM_ERROR @ 3702.423010 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 3702.423010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 29890053468664025737992595273942610091644587993853116481765771304303461593088 342
UVM_ERROR @ 7015.834224 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7015.834224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 57741230218091526289725841620250717583542310690676396230400259829893281177282 316
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3673.773480 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3673.773480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 92696766449195901777224088605352090619047455837256024636887217260122200422329 282
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 40660148268897086628177959097093603888977760476958657976811631495132736875913 369
UVM_ERROR @ 11221.003832 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 11221.003832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 76094322997421308948585999444830825511806853738243655193373238652814377932041 369
UVM_ERROR @ 12291.980474 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 12291.980474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 95819710011277356607390601527169318288097524677798506124276824878692202417906 341
UVM_ERROR @ 6443.192575 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 6443.192575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 21050982948137113116146009200556607945007213599428488158533226769669586074339 314
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 5820.892000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5820.892000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 17353449314427691695918538293531249774002511964702429641825477793559755044975 319
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 7658.827000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7658.827000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 637317642744479671767487955272658926701677570591737989489543002276160111367 332
UVM_ERROR @ 34537.037602 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34537.037602 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:412)] CHECK-fail: Expect alert *!
chip_sw_alert_test 42449530375981040455602885827919790517444506186447170895850816382860454948548 307
UVM_ERROR @ 2974.382590 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:412)] CHECK-fail: Expect alert 35!
UVM_INFO @ 2974.382590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 105045604010324489434214754470120526410602798638358684857073567658340372899001 308
UVM_ERROR @ 2720.105015 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2720.105015 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 6580922945105069624490606267288325488605459373601927802489929865562617292430 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 113017449258820603734387648206652703541251057334982157903380627360215447044423 343
UVM_ERROR @ 3292.152319 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 3292.152319 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 105416115828245408056675964878126580660536549594360754550481930798798215340659 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 114387012262683812122975171775401697542703050030559403514792145341629977275689 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 76316311500645224607236022109430467493031135287519913351029973630697770595584 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 37237033827278763500600719322359078259268213165667253778957860729640625222324 352
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 48761872858673337305432500071173049211451305155976658663166491787427248383644 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 53550995764598054668912735303269392508374155324417021907101515551770494002740 352
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 21620272916440192970441190441341812889556554281683190078907594552736495935512 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 97481370108728821031286173770981332261824810409770507421072916911008546958148 307
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 4498169470843059780920277192914431795449129100691801306791605288691743610118 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 23322440865018666366125628725448817213595061940330530611809114123484857596353 312
UVM_ERROR @ 2999.059000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 2999.059000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 102558779044619251588613398358780654453712292411935256388785390922997680331585 318
UVM_ERROR @ 3016.244000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3016.244000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 98528993934305334827968079850092637540354185821533347773518773699804032290801 327
UVM_ERROR @ 12934.363550 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 12934.363550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [power_virus_systemtest_sim_dv(sw/device/tests/power_virus_systemtest.c:343)] CHECK-fail: Unexpected IRQ fired with ID: *
chip_sw_power_virus 55557762395331643565433786446156514332092308481449629081947348300651928537413 331
UVM_ERROR @ 2300.565655 us: (sw_logger_if.sv:526) [power_virus_systemtest_sim_dv(sw/device/tests/power_virus_systemtest.c:343)] CHECK-fail: Unexpected IRQ fired with ID: 130
UVM_INFO @ 2300.565655 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 98632934195469831017384360765992678617663142998128044418585923524083853596992 351
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 69397973119351533611182788060923972013966465997324754708423033056180262519927 349
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 33790221233044690350511138125968138407929379111920076087127703734515099439 351
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 11904930692800827684703528939591041176150515222584003461784265091826139658631 349
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 22733787324495545528754287648814782163173151086085521474314401056239338406672 351
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 21734291905085359563827263964484489803729791138232660264407377713223537806499 349
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 74391686669636926838506521830720029905699847909981962936127080082576460520073 348
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 57842305276842696157252661687363756132227813269129956915488406826762692267416 348
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 103677074735952967511739199038639287707418370431826990339902325112120386031438 349
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 40894661025645161419416585630645260631562599035268379019719531325722567664308 349
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 15338541450027010046782452489490871311553641486037723020736966435363403992645 357
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 108240616504054679191482324218940225647086974234062683917582900147246528839814 359
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 98346274193577139142391990617528274326483941339334876699827061351794569126268 361
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 52677546874843223974191479302877991841617527379685066883696297100109140988532 323
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 5323752690693431209182735883431705031935535482320278937610050412245175420665 324
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 109229846465759406143416868997972154019605645567578468342784817186608475269710 325
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 83025072500116885123014189144560941249320316435155504256479408332319588881450 357
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 37174863324611033978711881601325740822278794540779780663205564115911335797996 323
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 12677916361854071207767132118318502225873642806528340918421195045197192094826 359
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 40046482700958396149973612829574472859853013075619844914938897039253514183921 323
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 42887174036568511084151168558674585019919208689515714828836503147691826236184 322
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 82404231954685019984841406663751118321311555589191051593842003774342683401513 325
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 38543555229007714910741191164058410146389671487682971092422186291898222026518 323
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 47947160252741964814976618682297896991432901572477889029957166197041325089467 325
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 66070775271449986453517626836733922662851497727543683515994241689381370567549 324
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'
rom_e2e_keymgr_init_rom_ext_meas 57262179995153716080436774864450932408188036661206281104949200502902264153936 317
Offending '(pend_req[h2d.a_source].pend == 0)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2627198145ps failed at 2627198145ps
Offending '(pend_req[h2d.a_source].pend == 0)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2627383473ps failed at 2627383473ps
Offending '(pend_req[h2d.a_source].pend == 0)'
Offending '$stable(key_data_i)'
rom_keymgr_functest 80936935059643969397915540552507581152420153014636508798638833693935279959066 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 4535.344850 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4535.344850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---