Simulation Results: clkmgr

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.77 %
  • code
  • 98.63 %
  • assert
  • 95.90 %
  • func
  • 86.79 %
  • line
  • 99.23 %
  • branch
  • 98.94 %
  • cond
  • 94.98 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.800s 29.875us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.820s 42.265us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.790s 75.304us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.620s 265.391us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.790s 345.827us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.410s 26.163us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.790s 75.304us 1 1 100.00
clkmgr_csr_aliasing 1.790s 345.827us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.660s 15.249us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.780s 56.527us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.020s 61.251us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.940s 157.875us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.800s 29.875us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 7.320s 2502.652us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 4.370s 1346.985us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 7.320s 2502.652us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 34.580s 6607.343us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.750s 31.124us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.850s 72.317us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.850s 72.317us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.820s 42.265us 1 1 100.00
clkmgr_csr_rw 0.790s 75.304us 1 1 100.00
clkmgr_csr_aliasing 1.790s 345.827us 1 1 100.00
clkmgr_same_csr_outstanding 0.890s 34.628us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.820s 42.265us 1 1 100.00
clkmgr_csr_rw 0.790s 75.304us 1 1 100.00
clkmgr_csr_aliasing 1.790s 345.827us 1 1 100.00
clkmgr_same_csr_outstanding 0.890s 34.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_tl_intg_err 1.810s 268.673us 1 1 100.00
clkmgr_sec_cm 5.620s 2155.251us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.600s 150.822us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.600s 150.822us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.600s 150.822us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.600s 150.822us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.570s 190.912us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.810s 268.673us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 7.320s 2502.652us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 4.370s 1346.985us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.600s 150.822us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.760s 56.694us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.910s 42.377us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.730s 23.417us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.790s 22.958us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.780s 37.427us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.790s 75.304us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 5.620s 2155.251us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 75.304us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 75.304us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 5.620s 2155.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.620s 794.880us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 140.550s 58499.218us 1 1 100.00