Simulation Results: csrng

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.92 %
  • code
  • 92.33 %
  • assert
  • 93.23 %
  • func
  • 75.20 %
  • block
  • 97.01 %
  • line
  • 97.80 %
  • branch
  • 92.50 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 88.594us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 52.590us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 49.259us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 21.000s 1084.338us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 23.904us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 53.230us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 49.259us 1 1 100.00
csrng_csr_aliasing 2.000s 23.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
alerts 1 1 100.00
csrng_alert 7.000s 405.384us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 4.000s 58.376us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 4.000s 58.376us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 69.000s 1683.170us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 90.405us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 51.893us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 123.339us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 123.339us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 52.590us 1 1 100.00
csrng_csr_rw 2.000s 49.259us 1 1 100.00
csrng_csr_aliasing 2.000s 23.904us 1 1 100.00
csrng_same_csr_outstanding 2.000s 77.627us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 52.590us 1 1 100.00
csrng_csr_rw 2.000s 49.259us 1 1 100.00
csrng_csr_aliasing 2.000s 23.904us 1 1 100.00
csrng_same_csr_outstanding 2.000s 77.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 4.000s 71.510us 1 1 100.00
csrng_sec_cm 3.000s 262.937us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 2.000s 49.259us 1 1 100.00
csrng_regwen 2.000s 32.581us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 7.000s 405.384us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 69.000s 1683.170us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
csrng_sec_cm 3.000s 262.937us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
csrng_sec_cm 3.000s 262.937us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
csrng_sec_cm 3.000s 262.937us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
csrng_sec_cm 3.000s 262.937us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
csrng_sec_cm 3.000s 262.937us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 7.000s 405.384us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 69.000s 1683.170us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 7.000s 405.384us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 71.510us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
csrng_sec_cm 3.000s 262.937us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
csrng_sec_cm 3.000s 262.937us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 136.602us 1 1 100.00
csrng_err 1.000s 25.540us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 62686870739714050266513248010481646375980082255623085370929420108669204974664 130
UVM_FATAL @ 58375715 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 272142243341467058217453688274777417556 [0xccbcb086e64dd698710a0cb6d7e22754])
UVM_INFO @ 58375715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
csrng_stress_all_with_rand_reset 17578016366215921565041009276632219094965407829104347509284636585040509195421 None
Job timed out after 180 minutes