Simulation Results: edn/edn0

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.72 %
  • code
  • 83.64 %
  • assert
  • 96.75 %
  • func
  • 79.76 %
  • line
  • 97.99 %
  • branch
  • 93.72 %
  • cond
  • 88.33 %
  • toggle
  • 85.45 %
  • FSM
  • 52.69 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 50.739us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.760s 23.702us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.850s 54.285us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.710s 1816.963us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.130s 22.793us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.110s 29.517us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.850s 54.285us 1 1 100.00
edn_csr_aliasing 1.130s 22.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.190s 52.216us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.190s 52.216us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.190s 52.216us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.790s 69.671us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.990s 26.041us 1 1 100.00
errs 1 1 100.00
edn_err 1.090s 49.191us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 21.911us 1 1 100.00
edn_disable_auto_req_mode 0.950s 27.604us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.310s 419.070us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.930s 12.360us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 19.787us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.060s 120.533us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.060s 120.533us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.760s 23.702us 1 1 100.00
edn_csr_rw 0.850s 54.285us 1 1 100.00
edn_csr_aliasing 1.130s 22.793us 1 1 100.00
edn_same_csr_outstanding 1.040s 21.693us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.760s 23.702us 1 1 100.00
edn_csr_rw 0.850s 54.285us 1 1 100.00
edn_csr_aliasing 1.130s 22.793us 1 1 100.00
edn_same_csr_outstanding 1.040s 21.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.570s 192.616us 1 1 100.00
edn_sec_cm 5.330s 452.703us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 16.040us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.990s 26.041us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.330s 452.703us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.330s 452.703us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.330s 452.703us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.330s 452.703us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.990s 26.041us 1 1 100.00
edn_sec_cm 5.330s 452.703us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.990s 26.041us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.570s 192.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 63.940s 7581.425us 1 1 100.00