Simulation Results: edn/edn1

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.04 %
  • code
  • 82.26 %
  • assert
  • 97.14 %
  • func
  • 81.72 %
  • line
  • 97.80 %
  • branch
  • 92.42 %
  • cond
  • 90.54 %
  • toggle
  • 86.20 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.970s 76.320us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.920s 28.825us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 30.538us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.390s 236.334us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.950s 85.211us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.290s 36.595us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 30.538us 1 1 100.00
edn_csr_aliasing 0.950s 85.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.160s 43.206us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.160s 43.206us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.160s 43.206us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.790s 26.875us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 245.553us 1 1 100.00
errs 1 1 100.00
edn_err 0.910s 29.629us 1 1 100.00
disable 2 2 100.00
edn_disable 0.940s 12.064us 1 1 100.00
edn_disable_auto_req_mode 1.110s 65.789us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.410s 1011.266us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.790s 27.237us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.810s 20.924us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.140s 85.750us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.140s 85.750us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.920s 28.825us 1 1 100.00
edn_csr_rw 0.790s 30.538us 1 1 100.00
edn_csr_aliasing 0.950s 85.211us 1 1 100.00
edn_same_csr_outstanding 0.920s 23.844us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.920s 28.825us 1 1 100.00
edn_csr_rw 0.790s 30.538us 1 1 100.00
edn_csr_aliasing 0.950s 85.211us 1 1 100.00
edn_same_csr_outstanding 0.920s 23.844us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 2.460s 175.501us 1 1 100.00
edn_sec_cm 3.450s 640.344us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 35.586us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 245.553us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.450s 640.344us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.450s 640.344us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.450s 640.344us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.450s 640.344us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 245.553us 1 1 100.00
edn_sec_cm 3.450s 640.344us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 245.553us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.460s 175.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 77.170s 18489.179us 1 1 100.00