Simulation Results: flash_ctrl

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.47 %
  • code
  • 94.14 %
  • assert
  • 96.76 %
  • func
  • 95.51 %
  • line
  • 95.97 %
  • branch
  • 97.16 %
  • cond
  • 93.48 %
  • toggle
  • 97.71 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 74.610s 72.523us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.540s 16.132us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 18.670s 73.120us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 5.540s 38.498us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 64.570s 34425.856us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 24.230s 1286.927us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.180s 119.377us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 5.540s 38.498us 1 1 100.00
flash_ctrl_csr_aliasing 24.230s 1286.927us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 8.350s 36.632us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 8.790s 18.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 9.470s 71.268us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 17.950s 110.356us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1199.710s 272294.681us 1 1 100.00
flash_ctrl_hw_rma_reset 744.760s 540367.564us 1 1 100.00
flash_ctrl_lcmgr_intg 7.290s 42.852us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1257.700s 308357.834us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 343.110s 19381.920us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 7.760s 61.706us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2567.710s 1564933.683us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 41.890s 71.911us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 14.230s 47.071us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.890s 30.156us 1 1 100.00
flash_ctrl_re_evict 21.140s 87.877us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 76.640s 413.576us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 76.640s 413.576us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 222.960s 47303.306us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 18.790s 295.970us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 124.230s 86.236us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 371.230s 15912.614us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 280.580s 2873.497us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 604.130s 1175.625us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.640s 23.135us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 117.080s 2962.572us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.420s 22.374us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 10.230s 23.639us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 578.510s 787.380us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 58.170s 8475.195us 1 1 100.00
flash_ctrl_otp_reset 58.240s 40.504us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1199.710s 272294.681us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 122.090s 3524.014us 1 1 100.00
flash_ctrl_intr_wr 46.410s 6945.279us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 188.090s 36183.497us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 114.470s 20999.019us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 48.720s 8468.555us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 42.100s 9151.237us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 22.470s 26.903us 1 1 100.00
flash_ctrl_ro_derr 110.210s 10082.429us 1 1 100.00
flash_ctrl_rw_derr 183.670s 4043.954us 1 1 100.00
flash_ctrl_derr_detect 112.640s 1007.808us 1 1 100.00
flash_ctrl_integrity 477.270s 9100.374us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 9.950s 24.996us 1 1 100.00
flash_ctrl_ro_serr 96.220s 7625.543us 1 1 100.00
flash_ctrl_rw_serr 111.180s 1061.490us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 38.880s 598.508us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 58.360s 3437.281us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 120.820s 10206.717us 1 1 100.00
flash_ctrl_write_word_sweep 10.530s 230.148us 1 1 100.00
flash_ctrl_read_word_sweep 6.320s 38.114us 1 1 100.00
flash_ctrl_ro 78.210s 1101.705us 1 1 100.00
flash_ctrl_rw 355.050s 4005.997us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.030s 943.803us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 603.280s 82163.736us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 28.840s 10063.253us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 9.920s 26.860us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.090s 30.824us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 7.460s 143.884us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 7.460s 143.884us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.670s 73.120us 1 1 100.00
flash_ctrl_csr_rw 5.540s 38.498us 1 1 100.00
flash_ctrl_csr_aliasing 24.230s 1286.927us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.140s 203.454us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.670s 73.120us 1 1 100.00
flash_ctrl_csr_rw 5.540s 38.498us 1 1 100.00
flash_ctrl_csr_aliasing 24.230s 1286.927us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.140s 203.454us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 18.300s 35.974us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 18.300s 35.974us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 18.300s 35.974us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 18.300s 35.974us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 15.270s 56.919us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 195.930s 1684.323us 1 1 100.00
flash_ctrl_sec_cm 1570.220s 917.115us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 195.930s 1684.323us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 195.930s 1684.323us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.090s 63.089us 1 1 100.00
flash_ctrl_wr_intg 7.360s 292.718us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 74.610s 72.523us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 58.240s 40.504us 1 1 100.00
flash_ctrl_disable 10.420s 22.374us 1 1 100.00
flash_ctrl_sec_info_access 52.450s 9112.127us 1 1 100.00
flash_ctrl_connect 10.230s 23.639us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 7.350s 22.392us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.540s 38.498us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 18.300s 35.974us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.540s 38.498us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 18.300s 35.974us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.540s 38.498us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 18.300s 35.974us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.420s 22.374us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.090s 63.089us 1 1 100.00
flash_ctrl_access_after_disable 5.830s 40.645us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.610s 30.663us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.420s 22.374us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 18.790s 295.970us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 355.050s 4005.997us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 111.180s 1061.490us 1 1 100.00
flash_ctrl_rw_derr 183.670s 4043.954us 1 1 100.00
flash_ctrl_integrity 477.270s 9100.374us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1199.710s 272294.681us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1570.220s 917.115us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1570.220s 917.115us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1570.220s 917.115us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1570.220s 917.115us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.460s 1001.055us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 8.220s 5.755us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 8.320s 24.145us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1570.220s 917.115us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1570.220s 917.115us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1570.220s 917.115us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.750s 410.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 229.180s 1925.168us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
flash_ctrl_phy_host_grant_err 89157421066046383533472048002272262867598517089415202807634675430385282369459 125
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
UVM_ERROR @ 5755.2 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 5755.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---