Simulation Results: hmac

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.54 %
  • code
  • 97.95 %
  • assert
  • 96.70 %
  • func
  • 43.96 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.46 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.140s 207.444us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.980s 72.683us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.920s 30.849us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.260s 534.694us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.540s 2414.324us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.090s 66.428us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.920s 30.849us 1 1 100.00
hmac_csr_aliasing 6.540s 2414.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 47.700s 19978.301us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 31.140s 2715.798us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 191.960s 12154.510us 1 1 100.00
hmac_test_sha384_vectors 312.750s 8947.311us 1 1 100.00
hmac_test_sha512_vectors 18.560s 446.132us 1 1 100.00
hmac_test_hmac256_vectors 7.960s 257.523us 1 1 100.00
hmac_test_hmac384_vectors 5.710s 1849.110us 1 1 100.00
hmac_test_hmac512_vectors 11.420s 3805.157us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 4.190s 203.246us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 15.120s 1488.273us 1 1 100.00
error 1 1 100.00
hmac_error 86.560s 7520.120us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 104.560s 16489.260us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.140s 207.444us 1 1 100.00
hmac_long_msg 47.700s 19978.301us 1 1 100.00
hmac_back_pressure 31.140s 2715.798us 1 1 100.00
hmac_datapath_stress 15.120s 1488.273us 1 1 100.00
hmac_burst_wr 4.190s 203.246us 1 1 100.00
hmac_stress_all 167.770s 4328.337us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.140s 207.444us 1 1 100.00
hmac_long_msg 47.700s 19978.301us 1 1 100.00
hmac_back_pressure 31.140s 2715.798us 1 1 100.00
hmac_datapath_stress 15.120s 1488.273us 1 1 100.00
hmac_wipe_secret 104.560s 16489.260us 1 1 100.00
hmac_test_sha256_vectors 191.960s 12154.510us 1 1 100.00
hmac_test_sha384_vectors 312.750s 8947.311us 1 1 100.00
hmac_test_sha512_vectors 18.560s 446.132us 1 1 100.00
hmac_test_hmac256_vectors 7.960s 257.523us 1 1 100.00
hmac_test_hmac384_vectors 5.710s 1849.110us 1 1 100.00
hmac_test_hmac512_vectors 11.420s 3805.157us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.140s 207.444us 1 1 100.00
hmac_long_msg 47.700s 19978.301us 1 1 100.00
hmac_back_pressure 31.140s 2715.798us 1 1 100.00
hmac_datapath_stress 15.120s 1488.273us 1 1 100.00
hmac_burst_wr 4.190s 203.246us 1 1 100.00
hmac_error 86.560s 7520.120us 1 1 100.00
hmac_wipe_secret 104.560s 16489.260us 1 1 100.00
hmac_test_sha256_vectors 191.960s 12154.510us 1 1 100.00
hmac_test_sha384_vectors 312.750s 8947.311us 1 1 100.00
hmac_test_sha512_vectors 18.560s 446.132us 1 1 100.00
hmac_test_hmac256_vectors 7.960s 257.523us 1 1 100.00
hmac_test_hmac384_vectors 5.710s 1849.110us 1 1 100.00
hmac_test_hmac512_vectors 11.420s 3805.157us 1 1 100.00
hmac_stress_all 167.770s 4328.337us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 167.770s 4328.337us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.670s 104.626us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.820s 55.786us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.480s 115.591us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.480s 115.591us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.980s 72.683us 1 1 100.00
hmac_csr_rw 0.920s 30.849us 1 1 100.00
hmac_csr_aliasing 6.540s 2414.324us 1 1 100.00
hmac_same_csr_outstanding 1.020s 43.700us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.980s 72.683us 1 1 100.00
hmac_csr_rw 0.920s 30.849us 1 1 100.00
hmac_csr_aliasing 6.540s 2414.324us 1 1 100.00
hmac_same_csr_outstanding 1.020s 43.700us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 1.630s 355.136us 1 1 100.00
hmac_sec_cm 0.870s 333.734us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.630s 355.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.140s 207.444us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.780s 350.755us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 141.790s 10717.755us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 39.027us 1 1 100.00