| V1 |
|
100.00% |
| V2 |
|
87.80% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_smoke | 1 | 1 | 100.00 | |||
| i2c_host_smoke | 46.250s | 2826.689us | 1 | 1 | 100.00 | |
| target_smoke | 1 | 1 | 100.00 | |||
| i2c_target_smoke | 6.090s | 1302.123us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| i2c_csr_hw_reset | 0.870s | 126.206us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| i2c_csr_rw | 0.910s | 62.576us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| i2c_csr_bit_bash | 3.430s | 1467.202us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| i2c_csr_aliasing | 1.400s | 42.971us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| i2c_csr_mem_rw_with_rand_reset | 0.840s | 44.526us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| i2c_csr_rw | 0.910s | 62.576us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 1.400s | 42.971us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_error_intr | 0 | 1 | 0.00 | |||
| i2c_host_error_intr | 0.760s | 14.762us | 0 | 1 | 0.00 | |
| host_stress_all | 0 | 1 | 0.00 | |||
| i2c_host_stress_all | 39.270s | 3050.301us | 0 | 1 | 0.00 | |
| host_maxperf | 1 | 1 | 100.00 | |||
| i2c_host_perf | 171.170s | 18596.259us | 1 | 1 | 100.00 | |
| host_override | 1 | 1 | 100.00 | |||
| i2c_host_override | 0.670s | 39.444us | 1 | 1 | 100.00 | |
| host_fifo_watermark | 1 | 1 | 100.00 | |||
| i2c_host_fifo_watermark | 35.440s | 10476.176us | 1 | 1 | 100.00 | |
| host_fifo_overflow | 1 | 1 | 100.00 | |||
| i2c_host_fifo_overflow | 46.070s | 33010.672us | 1 | 1 | 100.00 | |
| host_fifo_reset | 3 | 3 | 100.00 | |||
| i2c_host_fifo_reset_fmt | 0.950s | 124.306us | 1 | 1 | 100.00 | |
| i2c_host_fifo_fmt_empty | 6.370s | 444.438us | 1 | 1 | 100.00 | |
| i2c_host_fifo_reset_rx | 2.260s | 712.629us | 1 | 1 | 100.00 | |
| host_fifo_full | 1 | 1 | 100.00 | |||
| i2c_host_fifo_full | 38.570s | 4537.528us | 1 | 1 | 100.00 | |
| host_timeout | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 7.760s | 1331.536us | 1 | 1 | 100.00 | |
| i2c_host_mode_toggle | 0 | 1 | 0.00 | |||
| i2c_host_mode_toggle | 1.020s | 61.949us | 0 | 1 | 0.00 | |
| target_glitch | 0 | 1 | 0.00 | |||
| i2c_target_glitch | 2.080s | 567.307us | 0 | 1 | 0.00 | |
| target_stress_all | 1 | 1 | 100.00 | |||
| i2c_target_stress_all | 135.490s | 51039.894us | 1 | 1 | 100.00 | |
| target_maxperf | 1 | 1 | 100.00 | |||
| i2c_target_perf | 4.450s | 1821.877us | 1 | 1 | 100.00 | |
| target_fifo_empty | 2 | 2 | 100.00 | |||
| i2c_target_stress_rd | 27.010s | 1282.169us | 1 | 1 | 100.00 | |
| i2c_target_intr_smoke | 4.330s | 1667.790us | 1 | 1 | 100.00 | |
| target_fifo_reset | 2 | 2 | 100.00 | |||
| i2c_target_fifo_reset_acq | 1.320s | 175.663us | 1 | 1 | 100.00 | |
| i2c_target_fifo_reset_tx | 1.130s | 255.815us | 1 | 1 | 100.00 | |
| target_fifo_full | 3 | 3 | 100.00 | |||
| i2c_target_stress_wr | 55.740s | 38263.383us | 1 | 1 | 100.00 | |
| i2c_target_stress_rd | 27.010s | 1282.169us | 1 | 1 | 100.00 | |
| i2c_target_intr_stress_wr | 15.250s | 8189.199us | 1 | 1 | 100.00 | |
| target_timeout | 1 | 1 | 100.00 | |||
| i2c_target_timeout | 3.960s | 1053.391us | 1 | 1 | 100.00 | |
| target_clock_stretch | 1 | 1 | 100.00 | |||
| i2c_target_stretch | 1.840s | 219.854us | 1 | 1 | 100.00 | |
| bad_address | 1 | 1 | 100.00 | |||
| i2c_target_bad_addr | 2.260s | 2306.807us | 1 | 1 | 100.00 | |
| target_mode_glitch | 0 | 1 | 0.00 | |||
| i2c_target_hrst | 18.930s | 10004.683us | 0 | 1 | 0.00 | |
| target_fifo_watermark | 2 | 2 | 100.00 | |||
| i2c_target_fifo_watermarks_acq | 2.030s | 446.219us | 1 | 1 | 100.00 | |
| i2c_target_fifo_watermarks_tx | 1.140s | 97.088us | 1 | 1 | 100.00 | |
| host_mode_config_perf | 2 | 2 | 100.00 | |||
| i2c_host_perf | 171.170s | 18596.259us | 1 | 1 | 100.00 | |
| i2c_host_perf_precise | 1.210s | 48.059us | 1 | 1 | 100.00 | |
| host_mode_clock_stretching | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 7.760s | 1331.536us | 1 | 1 | 100.00 | |
| target_mode_tx_stretch_ctrl | 1 | 1 | 100.00 | |||
| i2c_target_tx_stretch_ctrl | 1.640s | 80.680us | 1 | 1 | 100.00 | |
| target_mode_nack_generation | 3 | 3 | 100.00 | |||
| i2c_target_nack_acqfull | 2.200s | 1687.494us | 1 | 1 | 100.00 | |
| i2c_target_nack_acqfull_addr | 1.560s | 1742.140us | 1 | 1 | 100.00 | |
| i2c_target_nack_txstretch | 1.080s | 147.193us | 1 | 1 | 100.00 | |
| host_mode_halt_on_nak | 1 | 1 | 100.00 | |||
| i2c_host_may_nack | 5.820s | 1684.399us | 1 | 1 | 100.00 | |
| target_mode_smbus_maxlen | 1 | 1 | 100.00 | |||
| i2c_target_smbus_maxlen | 1.610s | 475.399us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| i2c_alert_test | 0.620s | 16.978us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| i2c_intr_test | 0.880s | 26.122us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| i2c_tl_errors | 1.720s | 176.973us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| i2c_tl_errors | 1.720s | 176.973us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| i2c_csr_hw_reset | 0.870s | 126.206us | 1 | 1 | 100.00 | |
| i2c_csr_rw | 0.910s | 62.576us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 1.400s | 42.971us | 1 | 1 | 100.00 | |
| i2c_same_csr_outstanding | 0.950s | 73.796us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| i2c_csr_hw_reset | 0.870s | 126.206us | 1 | 1 | 100.00 | |
| i2c_csr_rw | 0.910s | 62.576us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 1.400s | 42.971us | 1 | 1 | 100.00 | |
| i2c_same_csr_outstanding | 0.950s | 73.796us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| i2c_tl_intg_err | 1.730s | 238.682us | 1 | 1 | 100.00 | |
| i2c_sec_cm | 0.890s | 327.663us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| i2c_tl_intg_err | 1.730s | 238.682us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_host_stress_all_with_rand_reset | 1.750s | 102.308us | 0 | 1 | 0.00 | |
| target_error_intr | 0 | 1 | 0.00 | |||
| i2c_target_unexp_stop | 0.910s | 56.182us | 0 | 1 | 0.00 | |
| target_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_target_stress_all_with_rand_reset | 7.100s | 2064.586us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between | ||||
| i2c_host_error_intr | 17078460712393071283530533979923986330145618724244543467090219992184475899103 | 86 |
UVM_ERROR @ 14762046 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 14762046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| i2c_host_stress_all | 90056550098176268762917159890031738674820755599192603689103841836431353095280 | 163 |
UVM_ERROR @ 3050300583 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 3050300583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| i2c_host_mode_toggle | 94536125997248312918557891559109121427888866525313651083857196964356485785935 | 81 |
UVM_ERROR @ 61948501 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 61948501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between | ||||
| i2c_target_glitch | 21198781509217818386119008029745213712207973287259383877045820609600755166249 | 84 |
UVM_ERROR @ 567307433 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 567307433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) | ||||
| i2c_target_unexp_stop | 39963766963169665917369730160498795243368314607452644445657330361739398847906 | 78 |
UVM_ERROR @ 56182236 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 56182236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! | ||||
| i2c_target_hrst | 39279796009908501583240626697054762314895671676987580472734992866457932988471 | 79 |
UVM_FATAL @ 10004683326 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10004683326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| i2c_host_stress_all_with_rand_reset | 64672371584428201360559550785723875795031477475424628181777936687985477603306 | 84 |
UVM_ERROR @ 102308328 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 102308328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| i2c_target_stress_all_with_rand_reset | 104517540245175139363333726227050884408578311325197794075862538481647987306894 | 86 |
UVM_ERROR @ 2064586118 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2064586118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|