Simulation Results: keymgr

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.54 %
  • code
  • 94.71 %
  • assert
  • 97.26 %
  • func
  • 64.66 %
  • line
  • 98.56 %
  • branch
  • 97.35 %
  • cond
  • 94.52 %
  • toggle
  • 97.06 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 3.100s 142.767us 1 1 100.00
random 1 1 100.00
keymgr_random 2.800s 86.226us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.930s 63.775us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.900s 268.344us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 5.430s 137.028us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 5.290s 124.059us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.500s 30.944us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.900s 268.344us 1 1 100.00
keymgr_csr_aliasing 5.290s 124.059us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 3.940s 310.275us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 3.360s 556.433us 1 1 100.00
keymgr_sideload_kmac 1.590s 26.720us 1 1 100.00
keymgr_sideload_aes 3.030s 878.836us 1 1 100.00
keymgr_sideload_otbn 4.750s 176.502us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.630s 37.019us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 1.880s 263.901us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.350s 208.041us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 4.030s 111.569us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 3.260s 195.789us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.880s 60.199us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 18.770s 2767.848us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.800s 59.208us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.980s 28.846us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.180s 60.206us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.180s 60.206us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.930s 63.775us 1 1 100.00
keymgr_csr_rw 0.900s 268.344us 1 1 100.00
keymgr_csr_aliasing 5.290s 124.059us 1 1 100.00
keymgr_same_csr_outstanding 2.230s 67.141us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.930s 63.775us 1 1 100.00
keymgr_csr_rw 0.900s 268.344us 1 1 100.00
keymgr_csr_aliasing 5.290s 124.059us 1 1 100.00
keymgr_same_csr_outstanding 2.230s 67.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 3.340s 496.732us 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.150s 89.565us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.150s 89.565us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.150s 89.565us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.150s 89.565us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 12.320s 519.346us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.340s 496.732us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.150s 89.565us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 3.940s 310.275us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 0.900s 268.344us 1 1 100.00
keymgr_random 2.800s 86.226us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 0.900s 268.344us 1 1 100.00
keymgr_random 2.800s 86.226us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 0.900s 268.344us 1 1 100.00
keymgr_random 2.800s 86.226us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 1.880s 263.901us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.260s 195.789us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.260s 195.789us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.800s 86.226us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.000s 310.800us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 1.600s 356.340us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 1.880s 263.901us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.600s 356.340us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.600s 356.340us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.600s 356.340us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.380s 240.376us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 1.600s 356.340us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 8.820s 597.353us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 6442193350955781078408229230108924710647960955879895712754495146760903863558 1315
UVM_ERROR @ 597352527 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 597352527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---