Simulation Results: kmac/unmasked

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.06 %
  • code
  • 89.21 %
  • assert
  • 97.90 %
  • func
  • 92.06 %
  • line
  • 97.39 %
  • branch
  • 95.20 %
  • cond
  • 92.39 %
  • toggle
  • 99.92 %
  • FSM
  • 61.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 21.420s 5430.311us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.860s 104.704us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.890s 29.513us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 5.630s 2399.991us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.350s 561.490us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.190s 24.005us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.890s 29.513us 1 1 100.00
kmac_csr_aliasing 5.350s 561.490us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.950s 24.492us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.450s 55.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 859.520s 51936.918us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 463.050s 9246.810us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1767.350s 352942.039us 1 1 100.00
kmac_test_vectors_sha3_256 31.160s 3409.948us 1 1 100.00
kmac_test_vectors_sha3_384 854.540s 25723.568us 1 1 100.00
kmac_test_vectors_sha3_512 10.960s 964.614us 1 1 100.00
kmac_test_vectors_shake_128 190.290s 195714.644us 1 1 100.00
kmac_test_vectors_shake_256 95.780s 17345.556us 1 1 100.00
kmac_test_vectors_kmac 2.230s 61.561us 1 1 100.00
kmac_test_vectors_kmac_xof 2.210s 137.237us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 165.180s 4744.165us 1 1 100.00
app 1 1 100.00
kmac_app 97.580s 7968.610us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 55.530s 2418.041us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 179.420s 14729.786us 1 1 100.00
error 1 1 100.00
kmac_error 109.770s 2204.097us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 2.860s 559.086us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 2.160s 108.646us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 11.110s 2320.456us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 4.190s 81.175us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 4.140s 517.928us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.330s 45.421us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 1108.710s 80491.970us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.820s 38.121us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.880s 50.592us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.060s 149.230us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.060s 149.230us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.860s 104.704us 1 1 100.00
kmac_csr_rw 0.890s 29.513us 1 1 100.00
kmac_csr_aliasing 5.350s 561.490us 1 1 100.00
kmac_same_csr_outstanding 1.230s 30.748us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.860s 104.704us 1 1 100.00
kmac_csr_rw 0.890s 29.513us 1 1 100.00
kmac_csr_aliasing 5.350s 561.490us 1 1 100.00
kmac_same_csr_outstanding 1.230s 30.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.710s 518.044us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.710s 518.044us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.710s 518.044us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.710s 518.044us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.730s 904.702us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 3.110s 428.647us 1 1 100.00
kmac_sec_cm 17.810s 8278.828us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.110s 428.647us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.330s 45.421us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 21.420s 5430.311us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 165.180s 4744.165us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.710s 518.044us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 17.810s 8278.828us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 17.810s 8278.828us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 17.810s 8278.828us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 21.420s 5430.311us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.330s 45.421us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 17.810s 8278.828us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 88.100s 2415.786us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 21.420s 5430.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 73.610s 10533.120us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 79517342384656683958470911123813971551974301180456527209387394791183163192914 365
UVM_ERROR @ 10533120071 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 10533120071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---