Simulation Results: lc_ctrl/volatile_unlock_disabled

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.70 %
  • code
  • 83.32 %
  • assert
  • 94.13 %
  • func
  • 91.64 %
  • line
  • 97.12 %
  • branch
  • 93.82 %
  • cond
  • 79.45 %
  • toggle
  • 86.42 %
  • FSM
  • 59.81 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.830s 50.784us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.790s 43.934us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.810s 34.697us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.980s 41.154us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 84.596us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.500s 31.737us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.810s 34.697us 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 84.596us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.700s 372.514us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.860s 307.286us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.740s 34.958us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.030s 1091.211us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.790s 203.652us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.640s 286.562us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.790s 203.652us 1 1 100.00
lc_ctrl_prog_failure 2.030s 1091.211us 1 1 100.00
lc_ctrl_errors 6.640s 286.562us 1 1 100.00
lc_ctrl_security_escalation 4.650s 736.645us 1 1 100.00
lc_ctrl_jtag_state_failure 29.820s 5038.631us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.650s 2385.660us 1 1 100.00
lc_ctrl_jtag_errors 43.570s 8569.424us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.190s 99.374us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.400s 131.602us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.140s 1530.098us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.560s 2241.933us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.420s 143.171us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.200s 72.565us 1 1 100.00
lc_ctrl_jtag_alert_test 0.830s 21.534us 1 1 100.00
lc_ctrl_jtag_smoke 4.590s 3324.282us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.910s 4213.986us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.650s 2385.660us 1 1 100.00
lc_ctrl_jtag_errors 43.570s 8569.424us 1 1 100.00
lc_ctrl_jtag_access 6.440s 915.575us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.100s 1677.234us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.770s 121.609us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.780s 47.526us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 19.580s 1307.440us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.860s 44.626us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.020s 249.204us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.020s 249.204us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.790s 43.934us 1 1 100.00
lc_ctrl_csr_rw 0.810s 34.697us 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 84.596us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.200s 39.810us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.790s 43.934us 1 1 100.00
lc_ctrl_csr_rw 0.810s 34.697us 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 84.596us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.200s 39.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 2.000s 133.858us 1 1 100.00
lc_ctrl_sec_cm 8.500s 660.725us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 133.858us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.860s 307.286us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.790s 203.652us 1 1 100.00
lc_ctrl_sec_cm 8.500s 660.725us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.790s 203.652us 1 1 100.00
lc_ctrl_sec_cm 8.500s 660.725us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.790s 203.652us 1 1 100.00
lc_ctrl_sec_cm 8.500s 660.725us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.790s 203.652us 1 1 100.00
lc_ctrl_sec_cm 8.500s 660.725us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.790s 203.652us 1 1 100.00
lc_ctrl_sec_cm 8.500s 660.725us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.790s 203.652us 1 1 100.00
lc_ctrl_sec_cm 8.500s 660.725us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.790s 203.652us 1 1 100.00
lc_ctrl_sec_cm 8.500s 660.725us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.790s 203.652us 1 1 100.00
lc_ctrl_sec_cm 8.500s 660.725us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.650s 736.645us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.700s 372.514us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.910s 4213.986us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.050s 437.102us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.050s 437.102us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.910s 5069.468us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.410s 1267.585us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.410s 1267.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 31.910s 2326.403us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 85996445663291727270637317268871424608565734823637025448824436441460017129383 4505
UVM_ERROR @ 2326402603 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2326402603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---