Simulation Results: lc_ctrl/volatile_unlock_enabled

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.81 %
  • code
  • 84.35 %
  • assert
  • 94.13 %
  • func
  • 93.95 %
  • line
  • 97.24 %
  • branch
  • 93.92 %
  • cond
  • 79.70 %
  • toggle
  • 86.38 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.730s 200.600us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.030s 92.628us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.890s 38.881us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.110s 187.778us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 20.050us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.950s 23.041us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.890s 38.881us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 20.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.800s 101.220us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.720s 391.813us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.910s 13.846us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.550s 216.298us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.640s 186.946us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.480s 1805.573us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.640s 186.946us 1 1 100.00
lc_ctrl_prog_failure 1.550s 216.298us 1 1 100.00
lc_ctrl_errors 4.480s 1805.573us 1 1 100.00
lc_ctrl_security_escalation 6.840s 2074.228us 1 1 100.00
lc_ctrl_jtag_state_failure 20.640s 2300.104us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.790s 1458.261us 1 1 100.00
lc_ctrl_jtag_errors 31.180s 7564.357us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.380s 93.087us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.090s 357.953us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 16.570s 4100.194us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 10.810s 4965.214us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.550s 995.787us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.690s 375.732us 1 1 100.00
lc_ctrl_jtag_alert_test 2.030s 685.927us 1 1 100.00
lc_ctrl_jtag_smoke 3.460s 587.478us 1 1 100.00
lc_ctrl_jtag_state_post_trans 18.450s 1883.232us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.790s 1458.261us 1 1 100.00
lc_ctrl_jtag_errors 31.180s 7564.357us 1 1 100.00
lc_ctrl_jtag_access 3.220s 142.237us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.390s 768.613us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 9.080s 1810.499us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 16.709us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 106.620s 46738.714us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.860s 52.828us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.770s 257.436us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.770s 257.436us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 92.628us 1 1 100.00
lc_ctrl_csr_rw 0.890s 38.881us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 20.050us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.970s 42.947us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 92.628us 1 1 100.00
lc_ctrl_csr_rw 0.890s 38.881us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 20.050us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.970s 42.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 2.250s 116.259us 1 1 100.00
lc_ctrl_sec_cm 6.610s 451.227us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.250s 116.259us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.720s 391.813us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.640s 186.946us 1 1 100.00
lc_ctrl_sec_cm 6.610s 451.227us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.640s 186.946us 1 1 100.00
lc_ctrl_sec_cm 6.610s 451.227us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.640s 186.946us 1 1 100.00
lc_ctrl_sec_cm 6.610s 451.227us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.640s 186.946us 1 1 100.00
lc_ctrl_sec_cm 6.610s 451.227us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.640s 186.946us 1 1 100.00
lc_ctrl_sec_cm 6.610s 451.227us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.640s 186.946us 1 1 100.00
lc_ctrl_sec_cm 6.610s 451.227us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.640s 186.946us 1 1 100.00
lc_ctrl_sec_cm 6.610s 451.227us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.640s 186.946us 1 1 100.00
lc_ctrl_sec_cm 6.610s 451.227us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.840s 2074.228us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.800s 101.220us 1 1 100.00
lc_ctrl_jtag_state_post_trans 18.450s 1883.232us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.850s 1734.820us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.850s 1734.820us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 11.940s 2297.542us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.820s 295.930us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.820s 295.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.700s 912.171us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 53297090302891096647186074227127768974260157836566153929242155888969894760412 154
UVM_ERROR @ 912171063 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 912171063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---