Simulation Results: otbn

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.53 %
  • code
  • 95.22 %
  • assert
  • 89.60 %
  • func
  • 95.76 %
  • block
  • 99.38 %
  • line
  • 99.57 %
  • branch
  • 91.99 %
  • toggle
  • 91.89 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 49.572us 1 1 100.00
single_binary 1 1 100.00
otbn_single 14.000s 130.600us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 14.994us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 14.961us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 344.602us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 16.463us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 26.440us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 14.961us 1 1 100.00
otbn_csr_aliasing 4.000s 16.463us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 69.000s 3448.099us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 15.000s 175.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 36.000s 495.575us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 49.000s 373.759us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 144.000s 722.420us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 79.000s 1551.217us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 12.000s 35.946us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 11.186us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 12.000s 64.595us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 20.857us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 131.010us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 334.514us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 334.514us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 14.994us 1 1 100.00
otbn_csr_rw 3.000s 14.961us 1 1 100.00
otbn_csr_aliasing 4.000s 16.463us 1 1 100.00
otbn_same_csr_outstanding 4.000s 366.380us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 14.994us 1 1 100.00
otbn_csr_rw 3.000s 14.961us 1 1 100.00
otbn_csr_aliasing 4.000s 16.463us 1 1 100.00
otbn_same_csr_outstanding 4.000s 366.380us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 68.573us 1 1 100.00
otbn_dmem_err 8.000s 18.272us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 10.000s 62.906us 1 1 100.00
otbn_controller_ispr_rdata_err 4.000s 31.484us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 224.477us 1 1 100.00
otbn_urnd_err 9.000s 78.042us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 27.249us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 40.400us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 53.996us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
otbn_tl_intg_err 9.000s 84.056us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 19.000s 405.457us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 49.572us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 8.000s 18.272us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 68.573us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 84.056us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 12.000s 35.946us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 68.573us 1 1 100.00
otbn_dmem_err 8.000s 18.272us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 11.186us 1 1 100.00
otbn_illegal_mem_acc 6.000s 27.249us 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 14.000s 130.600us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 68.573us 1 1 100.00
otbn_dmem_err 8.000s 18.272us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 11.186us 1 1 100.00
otbn_illegal_mem_acc 6.000s 27.249us 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 12.000s 35.946us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 68.573us 1 1 100.00
otbn_dmem_err 8.000s 18.272us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 11.186us 1 1 100.00
otbn_illegal_mem_acc 6.000s 27.249us 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 14.000s 130.600us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 84.940us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 12.827us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 47.000s 956.708us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 47.000s 956.708us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 26.554us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 262.962us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 31.446us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 31.446us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 10.798us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 14.000s 130.600us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 14.000s 130.600us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 14.000s 130.600us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 144.000s 722.420us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 14.000s 130.600us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 14.000s 130.600us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 72.018us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 14.000s 130.600us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 86.000s 2127.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 102.000s 2329.356us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 69.516us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 85507669113785800631584960517236443679224128811476238204654712117670843854168 213
UVM_FATAL @ 2329355650 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 2329355650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---