Simulation Results: otp_ctrl

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.89 %
  • code
  • 79.20 %
  • assert
  • 93.86 %
  • func
  • 72.62 %
  • line
  • 88.72 %
  • branch
  • 83.45 %
  • cond
  • 90.38 %
  • toggle
  • 88.31 %
  • FSM
  • 45.14 %
Validation stages
V1
100.00%
V2
90.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.550s 105.320us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.730s 259.033us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.450s 74.562us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.450s 65.523us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.920s 264.808us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.800s 98.843us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.030s 1132.461us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.450s 65.523us 1 1 100.00
otp_ctrl_csr_aliasing 2.800s 98.843us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.330s 39.840us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.290s 137.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 12.490s 323.933us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.030s 127.470us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 11.700s 14056.114us 1 1 100.00
otp_ctrl_check_fail 4.630s 245.714us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.790s 2990.395us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 4.220s 253.262us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 15.570s 938.297us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 10.650s 551.072us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 1.830s 723.618us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 5.800s 699.750us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 3.830s 519.641us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 89.570s 43596.948us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.320s 41.062us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.500s 59.795us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.770s 171.410us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.770s 171.410us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.450s 74.562us 1 1 100.00
otp_ctrl_csr_rw 1.450s 65.523us 1 1 100.00
otp_ctrl_csr_aliasing 2.800s 98.843us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.030s 114.330us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.450s 74.562us 1 1 100.00
otp_ctrl_csr_rw 1.450s 65.523us 1 1 100.00
otp_ctrl_csr_aliasing 2.800s 98.843us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.030s 114.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 13.000s 2056.358us 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 13.000s 2056.358us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.730s 259.033us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.730s 259.033us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
otp_ctrl_macro_errs 5.800s 699.750us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
otp_ctrl_macro_errs 5.800s 699.750us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.370s 151.935us 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.030s 127.470us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 4.630s 245.714us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 4.220s 253.262us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 4.220s 253.262us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 4.220s 253.262us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 4.220s 253.262us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 4.220s 253.262us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.730s 259.033us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 4.220s 253.262us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.730s 259.033us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.550s 15330.854us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.790s 2990.395us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.730s 259.033us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.730s 259.033us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 5.800s 699.750us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 14.320s 5865.092us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.380s 65.390us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_dai_errs 6192833106029694375435885341431113183565391636760114444868715358837059788224 1243
UVM_ERROR @ 723617852 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1757101381 [0x68bb3d45] vs 4223352189 [0xfbbb3d7d]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 723617852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 34428353395650388814382074089089858942910931630295412790958027041005123183370 1032
UVM_ERROR @ 699749893 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3724790517 [0xde03caf5] vs 3724790501 [0xde03cae5]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 699749893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 26429087963103711570199167461145237956558761718858609687453693308291076524999 92
UVM_ERROR @ 65389563 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 65389563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---