Simulation Results: pattgen

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 50.592us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 19.908us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 24.966us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 96.332us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 130.420us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 82.796us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 24.966us 1 1 100.00
pattgen_csr_aliasing 1.000s 130.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 32.000s 2797.049us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 30.000s 1452.208us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 33.957us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 1.000s 160.373us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 23.931us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 47.017us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 172.351us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 172.351us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 19.908us 1 1 100.00
pattgen_csr_rw 1.000s 24.966us 1 1 100.00
pattgen_csr_aliasing 1.000s 130.420us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 32.665us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 19.908us 1 1 100.00
pattgen_csr_rw 1.000s 24.966us 1 1 100.00
pattgen_csr_aliasing 1.000s 130.420us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 32.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 147.033us 1 1 100.00
pattgen_tl_intg_err 1.000s 101.507us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 101.507us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 12.000s 3111.292us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 90.000s 10004.850us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
pattgen_inactive_level 27503203059769624226934305388080304821717257438884063398716943792633029915980 99
UVM_FATAL @ 10004849564 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1e37f350, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10004849564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 62124316077905207820557162299789189186414843932155940442768400315462229902258 117
UVM_ERROR @ 1165053667 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1165055774 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1165055774 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1165222444 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]