| V1 |
|
100.00% |
| V2 |
|
86.67% |
| V2S |
|
80.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| pwrmgr_smoke | 0.630s | 62.931us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pwrmgr_csr_hw_reset | 0.640s | 46.666us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| pwrmgr_csr_rw | 0.610s | 20.052us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pwrmgr_csr_bit_bash | 1.930s | 72.710us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pwrmgr_csr_aliasing | 0.780s | 28.192us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| pwrmgr_csr_mem_rw_with_rand_reset | 0.720s | 64.172us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| pwrmgr_csr_rw | 0.610s | 20.052us | 1 | 1 | 100.00 | |
| pwrmgr_csr_aliasing | 0.780s | 28.192us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wakeup | 1 | 1 | 100.00 | |||
| pwrmgr_wakeup | 0.980s | 132.586us | 1 | 1 | 100.00 | |
| control_clks | 1 | 1 | 100.00 | |||
| pwrmgr_wakeup | 0.980s | 132.586us | 1 | 1 | 100.00 | |
| aborted_low_power | 2 | 2 | 100.00 | |||
| pwrmgr_aborted_low_power | 0.740s | 526.988us | 1 | 1 | 100.00 | |
| pwrmgr_lowpower_invalid | 0.680s | 45.179us | 1 | 1 | 100.00 | |
| reset | 1 | 2 | 50.00 | |||
| pwrmgr_reset | 0.630s | 25.346us | 1 | 1 | 100.00 | |
| pwrmgr_reset_invalid | 0.640s | 69.900us | 0 | 1 | 0.00 | |
| main_power_glitch_reset | 1 | 1 | 100.00 | |||
| pwrmgr_reset | 0.630s | 25.346us | 1 | 1 | 100.00 | |
| reset_wakeup_race | 1 | 1 | 100.00 | |||
| pwrmgr_wakeup_reset | 0.840s | 123.915us | 1 | 1 | 100.00 | |
| lowpower_wakeup_race | 1 | 1 | 100.00 | |||
| pwrmgr_lowpower_wakeup_race | 0.660s | 65.282us | 1 | 1 | 100.00 | |
| disable_rom_integrity_check | 1 | 1 | 100.00 | |||
| pwrmgr_disable_rom_integrity_check | 0.830s | 154.387us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| pwrmgr_stress_all | 10.070s | 10406.437us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| pwrmgr_intr_test | 0.600s | 49.914us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| pwrmgr_tl_errors | 2.230s | 1417.787us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| pwrmgr_tl_errors | 2.230s | 1417.787us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| pwrmgr_csr_hw_reset | 0.640s | 46.666us | 1 | 1 | 100.00 | |
| pwrmgr_csr_rw | 0.610s | 20.052us | 1 | 1 | 100.00 | |
| pwrmgr_csr_aliasing | 0.780s | 28.192us | 1 | 1 | 100.00 | |
| pwrmgr_same_csr_outstanding | 0.660s | 24.683us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| pwrmgr_csr_hw_reset | 0.640s | 46.666us | 1 | 1 | 100.00 | |
| pwrmgr_csr_rw | 0.610s | 20.052us | 1 | 1 | 100.00 | |
| pwrmgr_csr_aliasing | 0.780s | 28.192us | 1 | 1 | 100.00 | |
| pwrmgr_same_csr_outstanding | 0.660s | 24.683us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| pwrmgr_sec_cm | 0.630s | 6.479us | 0 | 1 | 0.00 | |
| pwrmgr_tl_intg_err | 0.800s | 11.370us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.630s | 6.479us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.630s | 6.479us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| pwrmgr_tl_intg_err | 0.800s | 11.370us | 0 | 1 | 0.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 1.430s | 873.907us | 1 | 1 | 100.00 | |
| sec_cm_rom_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| pwrmgr_wakeup_reset | 0.840s | 123.915us | 1 | 1 | 100.00 | |
| sec_cm_rstmgr_intersig_mubi | 1 | 1 | 100.00 | |||
| pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.730s | 192.365us | 1 | 1 | 100.00 | |
| sec_cm_esc_rx_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| pwrmgr_esc_clk_rst_malfunc | 0.580s | 31.455us | 1 | 1 | 100.00 | |
| sec_cm_esc_rx_clk_local_esc | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.630s | 6.479us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.630s | 6.479us | 0 | 1 | 0.00 | |
| sec_cm_fsm_terminal | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.630s | 6.479us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_flow_global_esc | 1 | 1 | 100.00 | |||
| pwrmgr_global_esc | 0.640s | 87.106us | 1 | 1 | 100.00 | |
| sec_cm_main_pd_rst_local_esc | 1 | 1 | 100.00 | |||
| pwrmgr_glitch | 0.600s | 43.559us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| pwrmgr_sec_cm_ctrl_config_regwen | 0.610s | 30.749us | 1 | 1 | 100.00 | |
| sec_cm_wakeup_config_regwen | 1 | 1 | 100.00 | |||
| pwrmgr_csr_rw | 0.610s | 20.052us | 1 | 1 | 100.00 | |
| sec_cm_reset_config_regwen | 1 | 1 | 100.00 | |||
| pwrmgr_csr_rw | 0.610s | 20.052us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| escalation_timeout | 0 | 1 | 0.00 | |||
| pwrmgr_escalation_timeout | 0.700s | 91.327us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| pwrmgr_stress_all_with_rand_reset | 4.830s | 1747.219us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A | ||||
| pwrmgr_escalation_timeout | 61959531107474604475427624513005946732612132966969138023402978639385942237537 | 75 |
UVM_ERROR @ 91326513 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 91326513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLowPower | ||||
| pwrmgr_reset_invalid | 89381622006354027416076407468793814595173464671522763327145290807695835424718 | 93 |
UVM_FATAL @ 69899916 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLowPower
UVM_INFO @ 69899916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire | ||||
| pwrmgr_sec_cm | 39934523521398804616042911669789441760211310022942748982876379977917411259247 | 78 |
UVM_ERROR @ 6479108 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 6479108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 79384550972613304349637710817346207249735645727107977646430187914785528537147 | 78 |
UVM_ERROR @ 11370181 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 11370181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! | ||||
| pwrmgr_stress_all | 16475828884844072397171525554613400935769397143353063427923011656784715322184 | 298 |
UVM_FATAL @ 10406436952 ps: (pwrmgr_reset_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] wait timeout occurred!
UVM_INFO @ 10406436952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|