Simulation Results: rom_ctrl/32kb

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.60 %
  • code
  • 96.59 %
  • assert
  • 96.80 %
  • func
  • 96.42 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.92 %
  • toggle
  • 100.00 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.990s 557.230us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.340s 136.854us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.100s 125.577us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.640s 125.710us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.180s 169.982us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.280s 527.648us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.100s 125.577us 1 1 100.00
rom_ctrl_csr_aliasing 4.180s 169.982us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.470s 533.825us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.850s 558.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.970s 916.450us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 8.970s 1140.835us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.060s 556.004us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.980s 632.436us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.720s 130.966us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.720s 130.966us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.340s 136.854us 1 1 100.00
rom_ctrl_csr_rw 4.100s 125.577us 1 1 100.00
rom_ctrl_csr_aliasing 4.180s 169.982us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.190s 338.188us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.340s 136.854us 1 1 100.00
rom_ctrl_csr_rw 4.100s 125.577us 1 1 100.00
rom_ctrl_csr_aliasing 4.180s 169.982us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.190s 338.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.610s 10770.892us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.660s 1304.916us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 100.840s 368.499us 1 1 100.00
rom_ctrl_tl_intg_err 49.130s 848.931us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 100.840s 368.499us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 100.840s 368.499us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.610s 10770.892us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.610s 10770.892us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.610s 10770.892us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.610s 10770.892us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.610s 10770.892us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 100.840s 368.499us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 100.840s 368.499us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.990s 557.230us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.990s 557.230us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.990s 557.230us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 49.130s 848.931us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.610s 10770.892us 1 1 100.00
rom_ctrl_kmac_err_chk 7.060s 556.004us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.610s 10770.892us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.610s 10770.892us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.610s 10770.892us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.660s 1304.916us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 100.840s 368.499us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 141.970s 8413.654us 1 1 100.00