Simulation Results: rom_ctrl/64kb

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.03 %
  • code
  • 99.43 %
  • assert
  • 96.80 %
  • func
  • 97.85 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.37 %
  • toggle
  • 99.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.000s 229.423us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.070s 537.036us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.200s 766.097us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.500s 297.896us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.120s 538.458us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.250s 318.689us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.200s 766.097us 1 1 100.00
rom_ctrl_csr_aliasing 7.120s 538.458us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.850s 216.132us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.170s 215.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.000s 540.831us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.230s 1073.739us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.380s 2947.990us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.080s 300.437us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.140s 725.966us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.140s 725.966us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.070s 537.036us 1 1 100.00
rom_ctrl_csr_rw 7.200s 766.097us 1 1 100.00
rom_ctrl_csr_aliasing 7.120s 538.458us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.020s 320.204us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.070s 537.036us 1 1 100.00
rom_ctrl_csr_rw 7.200s 766.097us 1 1 100.00
rom_ctrl_csr_aliasing 7.120s 538.458us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.020s 320.204us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.030s 2351.054us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.530s 2095.177us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_tl_intg_err 94.780s 1425.881us 1 1 100.00
rom_ctrl_sec_cm 224.090s 496.335us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 224.090s 496.335us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 224.090s 496.335us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.030s 2351.054us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.030s 2351.054us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.030s 2351.054us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.030s 2351.054us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.030s 2351.054us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 224.090s 496.335us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 224.090s 496.335us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.000s 229.423us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.000s 229.423us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.000s 229.423us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 94.780s 1425.881us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.030s 2351.054us 1 1 100.00
rom_ctrl_kmac_err_chk 13.380s 2947.990us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.030s 2351.054us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.030s 2351.054us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.030s 2351.054us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.530s 2095.177us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 224.090s 496.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 96.160s 11273.527us 1 1 100.00