Simulation Results: rstmgr

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.04 %
  • code
  • 99.46 %
  • assert
  • 98.13 %
  • func
  • 96.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.10 %
  • toggle
  • 99.41 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.360s 201.736us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.840s 124.412us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.730s 77.201us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.870s 1175.962us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.170s 357.159us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.410s 188.820us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.730s 77.201us 1 1 100.00
rstmgr_csr_aliasing 2.170s 357.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.130s 127.070us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.950s 489.455us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.130s 249.648us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.430s 1700.585us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.430s 1700.585us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.430s 1700.585us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.430s 1700.585us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 15.050s 4197.317us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.150s 98.656us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.830s 549.193us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.830s 549.193us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.840s 124.412us 1 1 100.00
rstmgr_csr_rw 0.730s 77.201us 1 1 100.00
rstmgr_csr_aliasing 2.170s 357.159us 1 1 100.00
rstmgr_same_csr_outstanding 1.350s 87.116us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.840s 124.412us 1 1 100.00
rstmgr_csr_rw 0.730s 77.201us 1 1 100.00
rstmgr_csr_aliasing 2.170s 357.159us 1 1 100.00
rstmgr_same_csr_outstanding 1.350s 87.116us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 11.990s 8571.097us 1 1 100.00
rstmgr_tl_intg_err 2.580s 952.742us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.990s 8571.097us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.990s 8571.097us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.580s 952.742us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.050s 142.458us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.150s 1970.588us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.630s 300.955us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.990s 8571.097us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.730s 77.201us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.730s 77.201us 1 1 100.00