Simulation Results: rv_timer

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.33 %
  • code
  • 100.00 %
  • assert
  • 95.22 %
  • func
  • 96.76 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.040s 355.902us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.680s 67.529us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.550s 38.416us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.410s 556.392us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.850s 27.646us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.780s 20.013us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.550s 38.416us 1 1 100.00
rv_timer_csr_aliasing 0.850s 27.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.820s 133.589us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.070s 1870.037us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 356.560s 281108.068us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 356.560s 281108.068us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.690s 87.161us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.610s 104.063us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.600s 10.849us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.630s 138.527us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.630s 138.527us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.680s 67.529us 1 1 100.00
rv_timer_csr_rw 0.550s 38.416us 1 1 100.00
rv_timer_csr_aliasing 0.850s 27.646us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 102.591us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.680s 67.529us 1 1 100.00
rv_timer_csr_rw 0.550s 38.416us 1 1 100.00
rv_timer_csr_aliasing 0.850s 27.646us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 102.591us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.850s 663.901us 1 1 100.00
rv_timer_tl_intg_err 0.970s 43.507us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.970s 43.507us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.640s 14.023us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.700s 252.507us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 38.510s 39924.281us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 9407043804213178659016851730418497605275583301964909990129024920905150301934 75
UVM_ERROR @ 252506768 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 252506768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 97157062291537695130899944456981400085067403935236598903279528117820733998729 75
UVM_FATAL @ 133589223 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd5547304) == 0x1
UVM_INFO @ 133589223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---