Simulation Results

Simulation Results: spi_device/1r1w

02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.48 %

code
93.22 %

assert
94.64 %

func
71.58 %

line
99.05 %

branch
98.25 %

cond
95.88 %

toggle
83.54 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		92.31%
V2S		100.00%
unmapped		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	16.200s	4682.765us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	1.040s	18.853us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	1.720s	118.215us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	26.030s	1803.638us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	5.720s	352.339us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	2.270s	2127.566us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	1.720s	118.215us	1	1	100.00
	spi_device_csr_aliasing	5.720s	352.339us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	0.820s	10.438us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	1.320s	21.511us	1	1	100.00

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	0.780s	57.291us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	0.770s	1.645us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	0.770s	4.128us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	1.450s	103.598us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	1.450s	103.598us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	2.400s	878.440us	1	1	100.00
	spi_device_tpm_sts_read	0.900s	27.434us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	22.810s	15131.977us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	5.400s	1544.940us	1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	3.090s	919.151us	1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	3.090s	919.151us	1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	12.660s	2093.901us	1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	12.660s	2093.901us	1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	12.660s	2093.901us	1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	12.660s	2093.901us	1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	12.660s	2093.901us	1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	7.230s	6838.491us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	7.450s	920.836us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	7.450s	920.836us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	7.450s	920.836us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	5.930s	347.101us	1	1	100.00
	spi_device_read_buffer_direct	5.470s	434.966us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	7.450s	920.836us	1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	62.430s	37092.589us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	4.430s	2610.035us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	4.430s	2610.035us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	16.200s	4682.765us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	40.230s	7883.681us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	173.990s	139053.760us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	0.720s	41.420us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	0.800s	18.132us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	1.560s	32.081us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	1.560s	32.081us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	1.040s	18.853us	1	1	100.00
	spi_device_csr_rw	1.720s	118.215us	1	1	100.00
	spi_device_csr_aliasing	5.720s	352.339us	1	1	100.00
	spi_device_same_csr_outstanding	2.760s	211.995us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	1.040s	18.853us	1	1	100.00
	spi_device_csr_rw	1.720s	118.215us	1	1	100.00
	spi_device_csr_aliasing	5.720s	352.339us	1	1	100.00
	spi_device_same_csr_outstanding	2.760s	211.995us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	5.500s	1244.324us	1	1	100.00
	spi_device_sec_cm	1.020s	42.884us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	5.500s	1244.324us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	92.650s	20698.218us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
	spi_device_mem_parity	19544068910707103623729963784000039556080061859119260697419839039997330044186	76	UVM_ERROR @ 1265122 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[42]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM_ERROR @ 1265122 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) UVM_ERROR @ 1265122 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[938]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	108340729422407747937027906071405393111306538540600019572690636534368568473677	76	UVM_ERROR @ 1864902 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8c0538 [100011000000010100111000] vs 0x0 [0]) UVM_ERROR @ 1930902 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x86897a [100001101000100101111010] vs 0x0 [0]) UVM_ERROR @ 1964902 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe6d725 [111001101101011100100101] vs 0x0 [0]) UVM_ERROR @ 2050902 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3031ed [1100000011000111101101] vs 0x0 [0]) UVM_ERROR @ 2053902 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc41ed9 [110001000001111011011001] vs 0x0 [0])