Simulation Results: spi_device/2p

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.79 %
  • code
  • 94.16 %
  • assert
  • 94.62 %
  • func
  • 71.58 %
  • line
  • 99.10 %
  • branch
  • 98.32 %
  • cond
  • 96.28 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 47.110s 4527.004us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.310s 65.547us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.830s 308.448us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.420s 724.221us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.630s 120.199us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.810s 358.161us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.830s 308.448us 1 1 100.00
spi_device_csr_aliasing 5.630s 120.199us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.690s 18.406us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.320s 24.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.890s 15.639us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.060s 106.393us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.850s 15.939us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.550s 289.414us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.550s 289.414us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.420s 832.274us 1 1 100.00
spi_device_tpm_sts_read 0.830s 40.856us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 14.620s 3387.548us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.080s 319.956us 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 11.100s 9563.808us 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 11.100s 9563.808us 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 4.970s 882.433us 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 4.970s 882.433us 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 4.970s 882.433us 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 4.970s 882.433us 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 4.970s 882.433us 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.020s 69.702us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 54.410s 13100.328us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 54.410s 13100.328us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 54.410s 13100.328us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.530s 283.519us 1 1 100.00
spi_device_read_buffer_direct 5.040s 547.356us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 54.410s 13100.328us 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 0.780s 74.314us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 11.530s 2146.442us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 11.530s 2146.442us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 47.110s 4527.004us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 19.730s 12370.375us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 96.380s 19285.349us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.760s 19.727us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.820s 14.231us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.670s 718.028us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.670s 718.028us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.310s 65.547us 1 1 100.00
spi_device_csr_rw 1.830s 308.448us 1 1 100.00
spi_device_csr_aliasing 5.630s 120.199us 1 1 100.00
spi_device_same_csr_outstanding 2.190s 163.655us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.310s 65.547us 1 1 100.00
spi_device_csr_rw 1.830s 308.448us 1 1 100.00
spi_device_csr_aliasing 5.630s 120.199us 1 1 100.00
spi_device_same_csr_outstanding 2.190s 163.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.860s 134.425us 1 1 100.00
spi_device_tl_intg_err 14.680s 823.238us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 14.680s 823.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 31.670s 14579.036us 1 1 100.00