Simulation Results: spi_host

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.79 %
  • code
  • 94.90 %
  • assert
  • 95.64 %
  • func
  • 87.82 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 93.05 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 15.000s 243.060us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 121.688us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 21.231us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 111.536us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 151.666us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 106.290us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 21.231us 1 1 100.00
spi_host_csr_aliasing 1.000s 151.666us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.818us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 51.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 24.128us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 38.000s 4415.616us 1 1 100.00
spi_host_error_cmd 1.000s 15.891us 1 1 100.00
spi_host_event 45.000s 1704.706us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 270.995us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 270.995us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 270.995us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 167.434us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 23.045us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 270.995us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 270.995us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 15.000s 243.060us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 15.000s 243.060us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 10.000s 835.589us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 289.806us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 35.000s 3098.551us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 90.023us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 38.000s 4415.616us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 52.330us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 24.593us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 542.068us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 542.068us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 121.688us 1 1 100.00
spi_host_csr_rw 1.000s 21.231us 1 1 100.00
spi_host_csr_aliasing 1.000s 151.666us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 42.078us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 121.688us 1 1 100.00
spi_host_csr_rw 1.000s 21.231us 1 1 100.00
spi_host_csr_aliasing 1.000s 151.666us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 42.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 123.702us 1 1 100.00
spi_host_tl_intg_err 1.000s 95.138us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 95.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
spi_host_upper_range_clkdiv 252.000s 61114.095us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_upper_range_clkdiv 108917759024388965757773361142096235889301426599764730691556057727416043043752 159
UVM_FATAL @ 61114094774 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 50000000ns spi_host_reg_block.status.active (addr=0x39a4a9d4, Comparison=CompareOpEq, exp_data=0x0, call_count=15
UVM_INFO @ 61114094774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---