Simulation Results: sram_ctrl/main

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.94 %
  • code
  • 95.88 %
  • assert
  • 95.83 %
  • func
  • 96.10 %
  • line
  • 99.11 %
  • branch
  • 97.52 %
  • cond
  • 92.04 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 12.580s 1708.665us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.640s 30.111us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.900s 41.758us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.020s 51.777us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 96.123us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.890s 360.724us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.900s 41.758us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 96.123us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 210.040s 21886.170us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 121.210s 10710.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 357.550s 17242.111us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 175.600s 17479.515us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1895.480s 836856.963us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 230.350s 11153.879us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 24.710s 26107.138us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 435.830s 8248.858us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 11.320s 567.417us 1 1 100.00
sram_ctrl_partial_access_b2b 281.440s 17906.182us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 48.760s 3071.030us 1 1 100.00
sram_ctrl_throughput_w_partial_write 42.850s 813.665us 1 1 100.00
sram_ctrl_throughput_w_readback 32.690s 885.064us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 45.140s 13613.424us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.580s 1401.328us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 4152.690s 440347.249us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.800s 73.953us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.090s 97.272us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.090s 97.272us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.640s 30.111us 1 1 100.00
sram_ctrl_csr_rw 0.900s 41.758us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 96.123us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.820s 20.712us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.640s 30.111us 1 1 100.00
sram_ctrl_csr_rw 0.900s 41.758us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 96.123us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.820s 20.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.760s 27114.274us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.480s 231.930us 1 1 100.00
sram_ctrl_sec_cm 0.990s 12.693us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.990s 12.693us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.480s 231.930us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 45.140s 13613.424us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 45.140s 13613.424us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.900s 41.758us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 435.830s 8248.858us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 435.830s 8248.858us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 435.830s 8248.858us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 24.710s 26107.138us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 8.110s 691.627us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.760s 27114.274us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.910s 2020.800us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 12.580s 1708.665us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 12.580s 1708.665us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 435.830s 8248.858us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.990s 12.693us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 24.710s 26107.138us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.990s 12.693us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.990s 12.693us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 12.580s 1708.665us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.990s 12.693us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 9.060s 2755.749us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 13478800856740854970648445373709169415611419975108969800187888539215745417581 102
UVM_ERROR @ 12693451 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 12693451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---