| V1 |
|
100.00% |
| V2 |
|
94.44% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| sysrst_ctrl_smoke | 1.130s | 2162.161us | 1 | 1 | 100.00 | |
| input_output_inverted | 1 | 1 | 100.00 | |||
| sysrst_ctrl_in_out_inverted | 3.420s | 2470.037us | 1 | 1 | 100.00 | |
| combo_detect_ec_rst | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst | 3.590s | 2210.838us | 1 | 1 | 100.00 | |
| combo_detect_ec_rst_with_pre_cond | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 5.880s | 2505.460us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 3.520s | 6071.747us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_rw | 1.690s | 2082.450us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_bit_bash | 59.360s | 52485.961us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_aliasing | 8.330s | 2966.628us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_mem_rw_with_rand_reset | 4.600s | 2076.719us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| sysrst_ctrl_csr_rw | 1.690s | 2082.450us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 8.330s | 2966.628us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| combo_detect | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect | 26.280s | 75165.938us | 1 | 1 | 100.00 | |
| combo_detect_with_pre_cond | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 65.600s | 132807.937us | 1 | 1 | 100.00 | |
| auto_block_key_outputs | 1 | 1 | 100.00 | |||
| sysrst_ctrl_auto_blk_key_output | 3.560s | 3155.328us | 1 | 1 | 100.00 | |
| keyboard_input_triggered_interrupt | 1 | 1 | 100.00 | |||
| sysrst_ctrl_edge_detect | 6.400s | 3199.379us | 1 | 1 | 100.00 | |
| pin_output_keyboard_inversion_control | 1 | 1 | 100.00 | |||
| sysrst_ctrl_pin_override_test | 5.760s | 2513.505us | 1 | 1 | 100.00 | |
| pin_input_value_accessibility | 1 | 1 | 100.00 | |||
| sysrst_ctrl_pin_access_test | 1.710s | 2248.762us | 1 | 1 | 100.00 | |
| ec_power_on_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_ec_pwr_on_rst | 2.600s | 3743.162us | 1 | 1 | 100.00 | |
| flash_write_protect_output | 1 | 1 | 100.00 | |||
| sysrst_ctrl_flash_wr_prot_out | 3.730s | 2615.341us | 1 | 1 | 100.00 | |
| ultra_low_power_test | 0 | 1 | 0.00 | |||
| sysrst_ctrl_ultra_low_pwr | 4.360s | 6277.582us | 0 | 1 | 0.00 | |
| sysrst_ctrl_feature_disable | 1 | 1 | 100.00 | |||
| sysrst_ctrl_feature_disable | 63.120s | 34933.385us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| sysrst_ctrl_stress_all | 242.190s | 121005.500us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_alert_test | 1.410s | 2082.430us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_intr_test | 4.550s | 2012.450us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_errors | 5.400s | 2025.424us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_errors | 5.400s | 2025.424us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 3.520s | 6071.747us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 1.690s | 2082.450us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 8.330s | 2966.628us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 20.400s | 9959.634us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 3.520s | 6071.747us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 1.690s | 2082.450us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 8.330s | 2966.628us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 20.400s | 9959.634us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| sysrst_ctrl_tl_intg_err | 45.830s | 22244.598us | 1 | 1 | 100.00 | |
| sysrst_ctrl_sec_cm | 19.540s | 22105.597us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_intg_err | 45.830s | 22244.598us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_stress_all_with_rand_reset | 11.770s | 11191.026us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error | ||||
| sysrst_ctrl_ultra_low_pwr | 1853852707367198367283475084978011605696261217110539254816568565747064720087 | 659 |
UVM_ERROR @ 6277554469 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 6277581867 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 6277581867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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