Simulation Results: uart

 
02/04/2026 19:24:53 DVSim: v1.17.3 sha: cd62ffa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.08 %
  • code
  • 96.47 %
  • assert
  • 97.12 %
  • func
  • 64.63 %
  • line
  • 99.48 %
  • branch
  • 97.67 %
  • cond
  • 97.20 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.410s 676.870us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.760s 1070.765us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.580s 24.477us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.630s 116.898us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.640s 86.804us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.640s 60.165us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.580s 24.477us 1 1 100.00
uart_csr_aliasing 0.640s 86.804us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 84.940s 76495.745us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.410s 676.870us 1 1 100.00
uart_tx_rx 84.940s 76495.745us 1 1 100.00
parity_error 2 2 100.00
uart_intr 63.920s 257884.834us 1 1 100.00
uart_rx_parity_err 74.260s 124742.560us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 84.940s 76495.745us 1 1 100.00
uart_intr 63.920s 257884.834us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 10.520s 38634.047us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 50.350s 84856.037us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 14.870s 66105.106us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 63.920s 257884.834us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 63.920s 257884.834us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 63.920s 257884.834us 1 1 100.00
perf 1 1 100.00
uart_perf 253.320s 28240.963us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.360s 2377.571us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.360s 2377.571us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 6.620s 42074.333us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.480s 5125.445us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.390s 517.898us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.370s 6259.891us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 136.330s 68898.156us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 474.960s 309865.172us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.610s 13.721us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.590s 167.564us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.620s 1763.524us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.620s 1763.524us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.760s 1070.765us 1 1 100.00
uart_csr_rw 0.580s 24.477us 1 1 100.00
uart_csr_aliasing 0.640s 86.804us 1 1 100.00
uart_same_csr_outstanding 0.680s 19.916us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.760s 1070.765us 1 1 100.00
uart_csr_rw 0.580s 24.477us 1 1 100.00
uart_csr_aliasing 0.640s 86.804us 1 1 100.00
uart_same_csr_outstanding 0.680s 19.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.800s 68.326us 1 1 100.00
uart_tl_intg_err 0.900s 53.104us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.900s 53.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 38.990s 8784.835us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *
uart_noise_filter 22549233297493541972417645457456072917784680987658999658769026094523843628625 77
UVM_ERROR @ 41330718739 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 41333949505 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 41333949505 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 41617026145 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 41617103068 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_stress_all_with_rand_reset 84800324998157478671776994823356570505046658802105678163745506678145286112118 176
UVM_ERROR @ 6462060003 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7, clk_pulses: 0
UVM_ERROR @ 6462080836 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6462101669 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (191 [0xbf] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 6462122502 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6462143335 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (191 [0xbf] vs 255 [0xff]) reg name: uart_reg_block.rdata