Simulation Results: adc_ctrl

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.26 %
  • code
  • 96.38 %
  • assert
  • 95.95 %
  • func
  • 18.44 %
  • line
  • 99.05 %
  • branch
  • 97.77 %
  • cond
  • 93.18 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 9.850s 5771.020us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.950s 831.881us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.360s 416.581us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 45.980s 45785.356us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.320s 1046.939us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.550s 552.317us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.360s 416.581us 1 1 100.00
adc_ctrl_csr_aliasing 1.320s 1046.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 268.000s 327245.459us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 191.940s 487860.674us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 193.270s 162648.686us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 101.850s 170514.127us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 79.330s 198846.395us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 242.330s 593030.658us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 271.830s 159551.129us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 116.360s 367766.528us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.380s 3869.646us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 16.460s 44675.852us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 106.970s 66015.137us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 206.250s 235654.656us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.750s 477.587us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.180s 293.886us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.690s 582.941us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.690s 582.941us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.950s 831.881us 1 1 100.00
adc_ctrl_csr_rw 1.360s 416.581us 1 1 100.00
adc_ctrl_csr_aliasing 1.320s 1046.939us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.600s 5195.138us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.950s 831.881us 1 1 100.00
adc_ctrl_csr_rw 1.360s 416.581us 1 1 100.00
adc_ctrl_csr_aliasing 1.320s 1046.939us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.600s 5195.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 2.950s 4349.097us 1 1 100.00
adc_ctrl_sec_cm 12.410s 7107.939us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.950s 4349.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 5.600s 11604.561us 1 1 100.00